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[Script] Add default net type option to example openfpga shell scripts

This commit is contained in:
tangxifan 2021-02-28 12:08:30 -07:00
parent c638e5bde5
commit d7eb159726
4 changed files with 4 additions and 4 deletions
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2
openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga
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@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric # Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist # - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose --default_net_type {OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
# Write the Verilog testbench for FPGA fabric # Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists # - We suggest the use of same output directory as fabric Verilog netlists

2
openfpga_flow/openfpga_shell_scripts/example_script.openfpga
View File

@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric # Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist # - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --default_net_type ${OPENFPGA_VERILOG_NET_TYPE} --verbose
# Write the Verilog testbench for FPGA fabric # Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists # - We suggest the use of same output directory as fabric Verilog netlists

2
openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga
View File

@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric # Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist # - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} --verbose
# Write the Verilog testbench for FPGA fabric # Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists # - We suggest the use of same output directory as fabric Verilog netlists

2
openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
View File

@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
# Write the Verilog netlist for FPGA fabric # Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist # - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template --verbose write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template --default_net_type {OPENFPGA_DEFAULT_NET_TYPE} --verbose
# Write the Verilog testbench for FPGA fabric # Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists # - We suggest the use of same output directory as fabric Verilog netlists