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[script] fixed some bugs

This commit is contained in:
tangxifan 2022-12-30 18:30:52 -08:00
parent 56a3e6e463
commit d7a95a8ec2
2 changed files with 6 additions and 4 deletions
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8
openfpga_flow/openfpga_shell_scripts/vpr_standalone_example_script.openfpga
View File

@ -1,13 +1,13 @@
# Run VPR for the 'and' design # Run VPR for the 'and' design
# Run packing stage only # Run packing stage only
vpr_standalone ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --pack vpr_standalone ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --pack --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH}
# Run placement stage only # Run placement stage only
vpr_standalone ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --place vpr_standalone ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --place --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH}
# Run routing # Run routing
vpr_standalone ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route vpr_standalone ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH}
# Run analysis as final results # Run analysis as final results
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --analysis vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --analysis --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH}
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
openfpga_flow/tasks/basic_tests/vpr_standalone/config/task.conf
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@ -19,6 +19,8 @@ fpga_flow=yosys_vpr
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/vpr_standalone_example_script.openfpga openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/vpr_standalone_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=20
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml