From d7967da32807f8174c7e0e71ef28891da4bc72e4 Mon Sep 17 00:00:00 2001
From: Nachiket Kapre <nachiket@uwaterloo.ca>
Date: Mon, 8 Feb 2021 23:04:00 -0500
Subject: [PATCH] bugfix in alt

---
 openfpga_flow/openfpga_cell_library/verilog/buf4.v | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/openfpga_flow/openfpga_cell_library/verilog/buf4.v b/openfpga_flow/openfpga_cell_library/verilog/buf4.v
index aadf7e5b5..a9f0585bc 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/buf4.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/buf4.v
@@ -1,16 +1,3 @@
-// ----- Verilog module for const0 -----
-module const0(const0);
-output [0:0] const0;
-assign const0[0] = 1'b0;
-endmodule
-
-// ----- Verilog module for const0 -----
-module const1(const1);
-output [0:0] const1;
-assign const1[0] = 1'b1;
-endmodule
-
-
 // ----- Verilog module for buf4 -----
 module buf4(in,
             out);