diff --git a/VERSION.md b/VERSION.md
index 0a029d233..992c7c678 100644
--- a/VERSION.md
+++ b/VERSION.md
@@ -1 +1 @@
-1.2.1785
+1.2.1795
diff --git a/docs/source/manual/file_formats/repack_design_constraints.rst b/docs/source/manual/file_formats/repack_design_constraints.rst
index 56f40c310..3c6eb9229 100644
--- a/docs/source/manual/file_formats/repack_design_constraints.rst
+++ b/docs/source/manual/file_formats/repack_design_constraints.rst
@@ -13,12 +13,17 @@ An example of design constraints is shown as follows.
 .. code-block:: xml
 
   <repack_design_constraints>
+    <pin_constraint pb_type="clb" pin="reset[0]" net="rst_n"/>
     <pin_constraint pb_type="clb" pin="clk[0]" net="clk0"/>
     <pin_constraint pb_type="clb" pin="clk[1]" net="clk1"/>
     <pin_constraint pb_type="clb" pin="clk[2]" net="OPEN"/>
     <pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/>
+    <ignore_net name="rst_n" pin="clb.I[0:11]"/>
   </repack_design_constraints>
 
+Pin constraint
+^^^^^^^^^^^^^^
+
 .. option:: pb_type="<string>"
 
   The pb_type name to be constrained, which should be consistent with VPR's architecture description.
@@ -32,3 +37,16 @@ An example of design constraints is shown as follows.
   The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file.
  
 .. warning:: Design constraints is a feature for power-users. It may cause repack to fail. It is users's responsibility to ensure proper design constraints
+
+Ignore net
+^^^^^^^^^^
+
+To ignore the global nets on specific pins, use the syntax ``ignore_net``. Note that the qualified pins are inputs, outputs, and clocks of pb_type. The option is useful for preventing global nets from being assigned to unwanted pins on pb_type.
+
+.. option:: name="<string>"
+   
+   The global nets's name to be ignored, which should be consistent with user-defined global nets in the PCF file. 
+
+.. option:: pin="<string>"
+   
+   The specified pins on a certain programmable block, which should be consistent with VPR's architecture description.
diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst
index ffd6d8087..a35f4d9ef 100644
--- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst
@@ -29,7 +29,8 @@ Repack's functionality are in the following aspects:
 
     Specify the mapping results of global nets should be ignored on which pins of a ``pb_type``. For example, ``--ignore_global_nets_on_pins clb.I[0:11]``. Once specified, the mapping results on the pins for all the global nets, such as clock, reset *etc.*, are ignored. Routing traces will be appeneded to other pins where the same global nets are mapped to. 
   
-  .. note:: This option is designed for global nets which are applied to both data path and global networks. For example, a reset signal is mapped to both a LUT input and the reset pin of a FF. Suggest not to use the option in other purposes!
+  .. note::  - This option is designed for global nets which are applied to both data path and global networks. For example, a reset signal is mapped to both a LUT input and the reset pin of a FF. Suggest not to use the option in other purposes!
+  - For repack options, the constraints specified by ``--ignore_global_nets_on_pins`` have higher priority than those set by ``ignore_net``. When the constraints from ``--ignore_global_nets_on_pins`` are satisfied, those from ``ignore_net`` will not be checked. For more information on ``ignore_net``, see :ref:`file_formats_repack_design_constraints`. 
 
   .. warning:: Users must specify the size/width of the pin. Currently, OpenFPGA cannot infer the pin size from the architecture!!!
      
diff --git a/yosys b/yosys
index 8bd681acf..2ffea67b0 160000
--- a/yosys
+++ b/yosys
@@ -1 +1 @@
-Subproject commit 8bd681acfc3b0913e57f6312ed357b2334cf19cb
+Subproject commit 2ffea67b043fcde3854618aca01a8aed0f41ec56