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Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later

This commit is contained in:
tangxifan 2019-09-13 15:36:35 -06:00
parent 009c0d63b5
commit d6fc9c1c71
1 changed files with 2 additions and 4 deletions
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6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp
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@ -288,8 +288,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir) {
/* TODO: Generate modules into a .bak file now. Rename after it is verified */
/* Plug in with the mux subckt */
std::string verilog_fname(submodule_dir + memories_verilog_file_name);
verilog_fname += ".bak";
@ -368,8 +367,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager,
/* Close the file stream */
fp.close();
/* TODO: Add fname to the linked list when debugging is finished */
/*
/* Add fname to the linked list
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
*/
}