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Merge pull request #1366 from lnis-uofu/xt_tile_module_port 

Now use relative index to name module ports of tile modules
This commit is contained in:
tangxifan 2023-09-21 10:45:38 -07:00 committed by GitHub
parent fda768bc4a f3279bd885
commit d6457489cf
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 12 additions and 22 deletions
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18
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -203,9 +203,8 @@ static int build_tile_module_port_and_nets_between_sb_and_pb(
std::string temp_sb_module_name = generate_switch_block_module_name(
fabric_tile.sb_coordinates(fabric_tile_id)[isb]);
if (name_module_using_index) {
temp_sb_module_name = generate_switch_block_module_name_using_index(
device_rr_gsb.get_sb_unique_module_index(
fabric_tile.sb_coordinates(fabric_tile_id)[isb]));
temp_sb_module_name =
generate_switch_block_module_name_using_index(isb);
}
src_grid_port.set_name(generate_tile_module_port_name(
temp_sb_module_name, sink_sb_port.get_name()));
@ -436,9 +435,7 @@ static int build_tile_module_port_and_nets_between_cb_and_pb(
cb_type, cb_inst_rr_gsb.get_cb_coordinate(cb_type));
if (name_module_using_index) {
cb_instance_name_in_tile =
generate_connection_block_module_name_using_index(
cb_type, device_rr_gsb.get_cb_unique_module_index(
cb_type, cb_inst_rr_gsb.get_cb_coordinate(cb_type)));
generate_connection_block_module_name_using_index(cb_type, icb);
}
src_cb_port.set_name(generate_tile_module_port_name(
cb_instance_name_in_tile, src_cb_port.get_name()));
@ -703,9 +700,8 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
std::string temp_sb_module_name = generate_switch_block_module_name(
fabric_tile.sb_coordinates(fabric_tile_id)[isb]);
if (name_module_using_index) {
temp_sb_module_name = generate_switch_block_module_name_using_index(
device_rr_gsb.get_sb_unique_module_index(
fabric_tile.sb_coordinates(fabric_tile_id)[isb]));
temp_sb_module_name =
generate_switch_block_module_name_using_index(isb);
}
chan_input_port.set_name(generate_tile_module_port_name(
temp_sb_module_name, chan_input_port.get_name()));
@ -925,9 +921,7 @@ static int build_tile_module_ports_from_cb(
cb_type, unique_rr_gsb.get_cb_coordinate(cb_type));
if (name_module_using_index) {
cb_instance_name_in_tile =
generate_connection_block_module_name_using_index(
cb_type, device_rr_gsb.get_cb_unique_module_index(
cb_type, unique_rr_gsb.get_cb_coordinate(cb_type)));
generate_connection_block_module_name_using_index(cb_type, icb);
}
vtr::Point<size_t> tile_coord =
fabric_tile.tile_coordinate(curr_fabric_tile_id);

14
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -306,8 +306,7 @@ static int build_top_module_tile_nets_between_sb_and_pb(
generate_switch_block_module_name(sink_sb_coord_in_unique_tile);
if (name_module_using_index) {
sink_sb_instance_name_in_unique_tile =
generate_switch_block_module_name_using_index(
device_rr_gsb.get_sb_unique_module_index(sink_sb_coord_in_unique_tile));
generate_switch_block_module_name_using_index(sb_idx_in_curr_fabric_tile);
}
/* We could have two different coordinators, one is the instance, the other is
@ -547,8 +546,7 @@ static int build_top_module_tile_nets_between_cb_and_pb(
if (name_module_using_index) {
src_cb_instance_name_in_unique_tile =
generate_connection_block_module_name_using_index(
cb_type, device_rr_gsb.get_cb_unique_module_index(
cb_type, src_cb_inst_rr_gsb.get_cb_coordinate(cb_type)));
cb_type, cb_idx_in_curr_fabric_tile);
}
/* We could have two different coordinators, one is the instance, the other is
@ -750,8 +748,7 @@ static int build_top_module_tile_nets_between_sb_and_cb(
generate_switch_block_module_name(sb_coord_in_unique_tile);
if (name_module_using_index) {
sb_instance_name_in_unique_tile =
generate_switch_block_module_name_using_index(
device_rr_gsb.get_sb_unique_module_index(sb_coord_in_unique_tile));
generate_switch_block_module_name_using_index(sb_idx_in_curr_fabric_tile);
}
/* Skip those Switch blocks that do not exist */
@ -856,9 +853,8 @@ static int build_top_module_tile_nets_between_sb_and_cb(
cb_type, unique_cb_rr_gsb.get_cb_coordinate(cb_type));
if (name_module_using_index) {
cb_instance_name_in_unique_tile =
generate_connection_block_module_name_using_index(
cb_type, device_rr_gsb.get_cb_unique_module_index(
cb_type, unique_cb_rr_gsb.get_cb_coordinate(cb_type)));
generate_connection_block_module_name_using_index(cb_type,
cb_idx_in_cb_tile);
}
std::string cb_tile_module_name =
generate_tile_module_name(cb_unique_tile_coord);

2
openfpga_flow/tasks/basic_tests/module_naming/using_index/config/task.conf
View File

@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_add_fpga_core_module=
openfpga_vpr_device=auto
openfpga_vpr_device=4x4
openfpga_vpr_route_chan_width=20
openfpga_fabric_module_name_options=--name_module_using_index