diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 1dbf64dc9..42ba377ed 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -61,6 +61,7 @@ int fpga_fabric_verilog(
   const DecoderLibrary &decoder_lib, const DeviceContext &device_ctx,
   const VprDeviceAnnotation &device_annotation,
   const DeviceRRGSB &device_rr_gsb, const FabricTile &fabric_tile,
+  const ModuleNameMap& module_name_map,
   const FabricVerilogOption &options) {
   vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n");
 
@@ -111,12 +112,12 @@ int fpga_fabric_verilog(
   /* Generate routing blocks */
   if (true == options.compress_routing()) {
     print_verilog_unique_routing_modules(
-      netlist_manager, const_cast<const ModuleManager &>(module_manager),
+      netlist_manager, const_cast<const ModuleManager &>(module_manager), module_name_map,
       device_rr_gsb, rr_dir_path, std::string(DEFAULT_RR_DIR_NAME), options);
   } else {
     VTR_ASSERT(false == options.compress_routing());
     print_verilog_flatten_routing_modules(
-      netlist_manager, const_cast<const ModuleManager &>(module_manager),
+      netlist_manager, const_cast<const ModuleManager &>(module_manager), module_name_map,
       device_rr_gsb, device_ctx.rr_graph, rr_dir_path,
       std::string(DEFAULT_RR_DIR_NAME), options);
   }
@@ -130,7 +131,7 @@ int fpga_fabric_verilog(
   /* Generate tiles */
   if (!fabric_tile.empty()) {
     status_code = print_verilog_tiles(
-      netlist_manager, const_cast<const ModuleManager &>(module_manager),
+      netlist_manager, const_cast<const ModuleManager &>(module_manager), module_name_map,
       tile_dir_path, fabric_tile, std::string(DEFAULT_TILE_DIR_NAME), options);
     if (status_code != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index bea3ba4d7..28c848be2 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -20,6 +20,7 @@
 #include "fabric_verilog_options.h"
 #include "io_location_map.h"
 #include "io_name_map.h"
+#include "module_name_map.h"
 #include "memory_bank_shift_register_banks.h"
 #include "module_manager.h"
 #include "mux_library.h"
@@ -45,6 +46,7 @@ int fpga_fabric_verilog(
   const DecoderLibrary& decoder_lib, const DeviceContext& device_ctx,
   const VprDeviceAnnotation& device_annotation,
   const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile,
+  const ModuleNameMap& module_name_map,
   const FabricVerilogOption& options);
 
 int fpga_verilog_full_testbench(
diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp
index 1cf57dabb..4b990d283 100644
--- a/openfpga/src/fpga_verilog/verilog_routing.cpp
+++ b/openfpga/src/fpga_verilog/verilog_routing.cpp
@@ -77,6 +77,7 @@ namespace openfpga {
  ********************************************************************/
 static void print_verilog_routing_connection_box_unique_module(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map,
   const std::string& subckt_dir, const std::string& subckt_dir_name,
   const RRGSB& rr_gsb, const t_rr_type& cb_type,
   const FabricVerilogOption& options) {
@@ -102,8 +103,8 @@ static void print_verilog_routing_connection_box_unique_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
-  ModuleId cb_module = module_manager.find_module(
-    generate_connection_block_module_name(cb_type, gsb_coordinate));
+  std::string cb_module_name = module_name_map.name(generate_connection_block_module_name(cb_type, gsb_coordinate));
+  ModuleId cb_module = module_manager.find_module(cb_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
 
   /* Write the verilog module */
@@ -191,6 +192,7 @@ static void print_verilog_routing_connection_box_unique_module(
  ********************************************************************/
 static void print_verilog_routing_switch_box_unique_module(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map,
   const std::string& subckt_dir, const std::string& subckt_dir_name,
   const RRGSB& rr_gsb, const FabricVerilogOption& options) {
   /* Create the netlist */
@@ -215,8 +217,9 @@ static void print_verilog_routing_switch_box_unique_module(
 
   /* Create a Verilog Module based on the circuit model, and add to module
    * manager */
+  std::string sb_module_name = module_name_map.name(generate_switch_block_module_name(gsb_coordinate));
   ModuleId sb_module = module_manager.find_module(
-    generate_switch_block_module_name(gsb_coordinate));
+    sb_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
 
   /* Write the verilog module */
@@ -279,6 +282,7 @@ static void print_verilog_flatten_connection_block_modules(
  *******************************************************************/
 void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
                                            const ModuleManager& module_manager,
+                                           const ModuleNameMap& module_name_map,
                                            const DeviceRRGSB& device_rr_gsb,
                                            const RRGraphView& rr_graph,
                                            const std::string& subckt_dir,
@@ -298,17 +302,17 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
         continue;
       }
       print_verilog_routing_switch_box_unique_module(
-        netlist_manager, module_manager, subckt_dir, subckt_dir_name, rr_gsb,
+        netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name, rr_gsb,
         options);
     }
   }
 
   print_verilog_flatten_connection_block_modules(
-    netlist_manager, module_manager, device_rr_gsb, subckt_dir, subckt_dir_name,
+    netlist_manager, module_manager, module_name_map, device_rr_gsb, subckt_dir, subckt_dir_name,
     CHANX, options);
 
   print_verilog_flatten_connection_block_modules(
-    netlist_manager, module_manager, device_rr_gsb, subckt_dir, subckt_dir_name,
+    netlist_manager, module_manager, module_name_map, device_rr_gsb, subckt_dir, subckt_dir_name,
     CHANY, options);
 }
 
@@ -324,6 +328,7 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
  *******************************************************************/
 void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
                                           const ModuleManager& module_manager,
+                                          const ModuleNameMap& module_name_map,
                                           const DeviceRRGSB& device_rr_gsb,
                                           const std::string& subckt_dir,
                                           const std::string& subckt_dir_name,
@@ -336,7 +341,7 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
   for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
     const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
     print_verilog_routing_switch_box_unique_module(
-      netlist_manager, module_manager, subckt_dir, subckt_dir_name,
+      netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name,
       unique_mirror, options);
   }
 
@@ -346,7 +351,7 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
     const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
 
     print_verilog_routing_connection_box_unique_module(
-      netlist_manager, module_manager, subckt_dir, subckt_dir_name,
+      netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name,
       unique_mirror, CHANX, options);
   }
 
@@ -356,7 +361,7 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
     const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
 
     print_verilog_routing_connection_box_unique_module(
-      netlist_manager, module_manager, subckt_dir, subckt_dir_name,
+      netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name,
       unique_mirror, CHANY, options);
   }
 
diff --git a/openfpga/src/fpga_verilog/verilog_routing.h b/openfpga/src/fpga_verilog/verilog_routing.h
index 2766c1b2a..15baa3ebb 100644
--- a/openfpga/src/fpga_verilog/verilog_routing.h
+++ b/openfpga/src/fpga_verilog/verilog_routing.h
@@ -8,6 +8,7 @@
 #include "device_rr_gsb.h"
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "mux_library.h"
 #include "netlist_manager.h"
 #include "rr_graph_view.h"
@@ -21,6 +22,7 @@ namespace openfpga {
 
 void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
                                            const ModuleManager& module_manager,
+                                           const ModuleNameMap& module_name_map,
                                            const DeviceRRGSB& device_rr_gsb,
                                            const RRGraphView& rr_graph,
                                            const std::string& subckt_dir,
@@ -29,6 +31,7 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
 
 void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
                                           const ModuleManager& module_manager,
+                                          const ModuleNameMap& module_name_map,
                                           const DeviceRRGSB& device_rr_gsb,
                                           const std::string& subckt_dir,
                                           const std::string& subckt_dir_name,
diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp
index 400695554..e66b9c317 100644
--- a/openfpga/src/fpga_verilog/verilog_tile.cpp
+++ b/openfpga/src/fpga_verilog/verilog_tile.cpp
@@ -26,13 +26,14 @@ namespace openfpga {
  *******************************************************************/
 static int print_verilog_tile_module_netlist(
   NetlistManager& netlist_manager, const ModuleManager& module_manager,
+  const ModuleNameMap& module_name_map,
   const std::string& verilog_dir, const FabricTile& fabric_tile,
   const FabricTileId& fabric_tile_id, const std::string& subckt_dir_name,
   const FabricVerilogOption& options) {
   /* Create a module as the top-level fabric, and add it to the module manager
    */
   vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(fabric_tile_id);
-  std::string tile_module_name = generate_tile_module_name(tile_coord);
+  std::string tile_module_name = module_name_map.name(generate_tile_module_name(tile_coord));
   ModuleId tile_module = module_manager.find_module(tile_module_name);
   if (!module_manager.valid_module_id(tile_module)) {
     return CMD_EXEC_FATAL_ERROR;
@@ -89,6 +90,7 @@ static int print_verilog_tile_module_netlist(
  *******************************************************************/
 int print_verilog_tiles(NetlistManager& netlist_manager,
                         const ModuleManager& module_manager,
+                        const ModuleNameMap& module_name_map,
                         const std::string& verilog_dir,
                         const FabricTile& fabric_tile,
                         const std::string& subckt_dir_name,
@@ -100,7 +102,7 @@ int print_verilog_tiles(NetlistManager& netlist_manager,
   /* Build a module for each unique tile  */
   for (FabricTileId fabric_tile_id : fabric_tile.unique_tiles()) {
     status_code = print_verilog_tile_module_netlist(
-      netlist_manager, module_manager, verilog_dir, fabric_tile, fabric_tile_id,
+      netlist_manager, module_manager, module_name_map, verilog_dir, fabric_tile, fabric_tile_id,
       subckt_dir_name, options);
     if (status_code != CMD_EXEC_SUCCESS) {
       return CMD_EXEC_FATAL_ERROR;
diff --git a/openfpga/src/fpga_verilog/verilog_tile.h b/openfpga/src/fpga_verilog/verilog_tile.h
index 03dac11ae..6fb6c63ef 100644
--- a/openfpga/src/fpga_verilog/verilog_tile.h
+++ b/openfpga/src/fpga_verilog/verilog_tile.h
@@ -9,6 +9,7 @@
 #include "fabric_tile.h"
 #include "fabric_verilog_options.h"
 #include "module_manager.h"
+#include "module_name_map.h"
 #include "netlist_manager.h"
 
 /********************************************************************
@@ -20,6 +21,7 @@ namespace openfpga {
 
 int print_verilog_tiles(NetlistManager& netlist_manager,
                         const ModuleManager& module_manager,
+                        const ModuleNameMap& module_name_map,
                         const std::string& verilog_dir,
                         const FabricTile& fabric_tile,
                         const std::string& subckt_dir_name,