riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA

This commit is contained in:
tangxifan 2024-06-26 21:52:45 -07:00
parent cab649893b
commit d5d9531eec
1 changed files with 13 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
openfpga/src/annotation/route_clock_rr_graph.cpp
View File

@ -175,15 +175,21 @@ static int route_clock_tree_rr_graph(
/* if the IPIN is mapped, only connect when net mapping is /* if the IPIN is mapped, only connect when net mapping is
* expected */ * expected */
if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) {
VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the tree is not used\n",
clk_ntwk.spine_name(ispine).c_str());
continue; continue;
} }
if (!vpr_routing_annotation.rr_node_net(des_node)) { //if (!vpr_routing_annotation.rr_node_net(des_node)) {
continue; // VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the IPIN is not mapped\n",
} // clk_ntwk.spine_name(ispine).c_str());
if (vpr_routing_annotation.rr_node_net(des_node) != // continue;
tree2clk_pin_map.at(ipin)) { //}
continue; //if (vpr_routing_annotation.rr_node_net(des_node) !=
} // tree2clk_pin_map.at(ipin)) {
// VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the net mapping does not match clock net\n",
// clk_ntwk.spine_name(ispine).c_str());
// continue;
//}
VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(src_node));
VTR_ASSERT(rr_graph.valid_node(des_node)); VTR_ASSERT(rr_graph.valid_node(des_node));
vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node,