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[doc] syntax

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tangxifan 2023-08-06 23:24:59 -07:00
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docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst
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@ -265,20 +265,21 @@ build_fabric
Group configuration memory blocks under each CLB/SB/CB etc. into a centralized configuration memory blocks, as depicted in :numref:`fig_group_config_block_overview`. When disabled, the configuration memory blocks are placed in a distributed way under CLB/SB/CB etc. For example, each programming resource, e.g., LUT, has a dedicated configuration memory block, being placed in the same module. When enabled, as illustrated in :numref:`fig_group_config_block_hierarchy`, the physical memory block locates under a CLB, driving a number of logical memory blocks which are close to the programmable resources. The logical memory blocks contain only pass-through wires which can be optimized out during physical design phase.
.. _fig_group_config_block_overview:
.. figure:: ./figures/group_config_block_overview.png
:width: 100%
Impact on grouping configuable blocks: before and after
.. _fig_group_config_block_hierarchy:
.. figure:: ./figures/group_config_block_hierarchy.png
:width: 100%
Netlist hierarchy on grouped configuable blocks
.. _fig_group_config_block_overview:
.. figure:: ./figures/group_config_block_overview.png
:width: 100%
Impact on grouping configuable blocks: before and after
.. _fig_group_config_block_hierarchy:
.. figure:: ./figures/group_config_block_hierarchy.png
:width: 100%
Netlist hierarchy on grouped configuable blocks
.. option:: --duplicate_grid_pin
Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed