From d3d81f0b1879d74fba196f06fe6993e24d521cfb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Aug 2022 21:05:50 -0700 Subject: [PATCH] [engine] keep adapting to latest VTR --- .../annotation/annotate_physical_tiles.cpp | 38 ++++++++++--------- .../src/annotation/annotate_placement.cpp | 2 +- openfpga/src/annotation/annotate_routing.cpp | 4 +- 3 files changed, 24 insertions(+), 20 deletions(-) diff --git a/openfpga/src/annotation/annotate_physical_tiles.cpp b/openfpga/src/annotation/annotate_physical_tiles.cpp index 4c95b0754..0cb8d93cd 100644 --- a/openfpga/src/annotation/annotate_physical_tiles.cpp +++ b/openfpga/src/annotation/annotate_physical_tiles.cpp @@ -22,23 +22,27 @@ void build_physical_tile_pin2port_info(const DeviceContext& vpr_device_ctx, vtr::ScopedStartFinishTimer timer("Build fast look-up for physical tile pins"); for (const t_physical_tile_type& physical_tile : vpr_device_ctx.physical_tile_types) { - /* Count the number of pins for each sub tile */ - int num_pins_per_subtile = 0; - for (const t_physical_tile_port& tile_port : physical_tile.ports) { - num_pins_per_subtile += tile_port.num_pins; - } - /* For each sub tile, the starting pin index is (num_pins_per_subtile * index) + abs_index */ - for (int subtile_index = 0; subtile_index < physical_tile.capacity; ++subtile_index) { - for (const t_physical_tile_port& tile_port : physical_tile.ports) { - for (int pin_index = 0; pin_index < tile_port.num_pins; ++pin_index) { - int absolute_pin_index = subtile_index * num_pins_per_subtile + tile_port.absolute_first_pin_index + pin_index; - BasicPort tile_port_info(tile_port.name, pin_index, pin_index); - vpr_device_annotation.add_physical_tile_pin2port_info_pair(&physical_tile, - absolute_pin_index, - tile_port_info); - vpr_device_annotation.add_physical_tile_pin_subtile_index(&physical_tile, - absolute_pin_index, - subtile_index); + int curr_pin_index = 0; + /* Walk through each subtile, consider their capacity and num of pins */ + for (const t_sub_tile& sub_tile : physical_tile.sub_tiles) { + /* Walk through capacity */ + for (int subtile_index = sub_tile.capacity.low; subtile_index < sub_tile.capacity.high; subtile_index++) { + /* For each sub tile, the starting pin index is (num_pins_per_subtile * index) + abs_index */ + for (const t_physical_tile_port& tile_port : sub_tile.ports) { + for (int pin_index = 0; pin_index < tile_port.num_pins; ++pin_index) { + int absolute_pin_index = curr_pin_index + tile_port.absolute_first_pin_index + pin_index; + BasicPort tile_port_info(tile_port.name, pin_index, pin_index); + vpr_device_annotation.add_physical_tile_pin2port_info_pair(&physical_tile, + absolute_pin_index, + tile_port_info); + vpr_device_annotation.add_physical_tile_pin_subtile_index(&physical_tile, + absolute_pin_index, + subtile_index); + } + } + /* Count the number of pins for each sub tile */ + for (const t_physical_tile_port& tile_port : sub_tile.ports) { + curr_pin_index += tile_port.num_pins; } } } diff --git a/openfpga/src/annotation/annotate_placement.cpp b/openfpga/src/annotation/annotate_placement.cpp index adc83d5ff..3f7179aaa 100644 --- a/openfpga/src/annotation/annotate_placement.cpp +++ b/openfpga/src/annotation/annotate_placement.cpp @@ -26,7 +26,7 @@ void annotate_mapped_blocks(const DeviceContext& device_ctx, place_annotation.init_mapped_blocks(device_ctx.grid); for (const ClusterBlockId& blk_id : cluster_ctx.clb_nlist.blocks()) { vtr::Point grid_coord(place_ctx.block_locs[blk_id].loc.x, place_ctx.block_locs[blk_id].loc.y); - place_annotation.add_mapped_block(grid_coord, place_ctx.block_locs[blk_id].loc.z, blk_id); + place_annotation.add_mapped_block(grid_coord, place_ctx.block_locs[blk_id].loc.sub_tile, blk_id); } VTR_LOG("Done\n"); } diff --git a/openfpga/src/annotation/annotate_routing.cpp b/openfpga/src/annotation/annotate_routing.cpp index 2015132a1..6819a40c2 100644 --- a/openfpga/src/annotation/annotate_routing.cpp +++ b/openfpga/src/annotation/annotate_routing.cpp @@ -36,7 +36,7 @@ void annotate_rr_node_nets(const DeviceContext& device_ctx, } t_trace* tptr = routing_ctx.trace[net_id].head; while (tptr != nullptr) { - RRNodeId rr_node = tptr->index; + RRNodeId rr_node = RRNodeId(tptr->index); /* Ignore source and sink nodes, they are the common node multiple starting and ending points */ if ( (SOURCE != device_ctx.rr_graph.node_type(rr_node)) && (SINK != device_ctx.rr_graph.node_type(rr_node)) ) { @@ -101,7 +101,7 @@ RRNodeId find_previous_node_from_routing_traces(const RRGraphView& rr_graph, if (false == valid_prev_node) { t_trace* tptr = routing_trace_head; while (tptr != nullptr) { - RRNodeId cand_prev_node = tptr->index; + RRNodeId cand_prev_node = RRNodeId(tptr->index); bool is_good_cand = false; for (const RREdgeId& in_edge : rr_graph.node_in_edges(cur_rr_node)) { if (cand_prev_node == rr_graph.edge_src_node(in_edge)) {