[core] now support rebuild configuarable children for ccff submodules

openfpga/src/fabric/module_manager.cpp

@@ -1320,6 +1320,15 @@ void ModuleManager::clear_io_children(const ModuleId& parent_module) {
   io_child_coordinates_[parent_module].clear();
 }
 
+void ModuleManager::clear_module_net_sinks(const ModuleId& parent_module,
+                                           const ModuleNetId& net) {
+  VTR_ASSERT(valid_module_net_id(parent_module, net));
+  net_sink_ids_[parent_module][net].clear();
+  net_sink_terminal_ids_[parent_module][net].clear();
+  net_sink_instance_ids_[parent_module][net].clear();
+  net_sink_pin_ids_[parent_module][net].clear();
+}
+
 /******************************************************************************
  * Private validators/invalidators
  ******************************************************************************/

openfpga/src/fabric/module_manager.h

@@ -469,6 +469,10 @@ class ModuleManager {
    */
   void clear_io_children(const ModuleId& parent_module);
 
+  /* Remove all the sinks for a given net under a module */
+  void clear_module_net_sinks(const ModuleId& parent_module,
+                              const ModuleNetId& net);
+
  public: /* Public validators/invalidators */
   bool valid_module_id(const ModuleId& module) const;
   bool valid_module_port_id(const ModuleId& module,

openfpga/src/utils/module_manager_utils.cpp

@@ -2652,6 +2652,334 @@ static bool update_submodule_memory_modules_from_fabric_key(
   return CMD_EXEC_SUCCESS;
 }
 
+/********************************************************************
+ * Remove the nets around the configuration chain (ccff_head and ccff_tails)
+ *******************************************************************/
+static int remove_submodule_nets_cmos_memory_chain_config_bus(
+  ModuleManager& module_manager, const ModuleId& parent_module,
+  const e_config_protocol_type& sram_orgz_type) {
+  for (size_t mem_index = 0;
+       mem_index < module_manager.configurable_children(parent_module).size();
+       ++mem_index) {
+    ModuleId net_src_module_id;
+    size_t net_src_instance_id;
+    ModulePortId net_src_port_id;
+
+    if (0 == mem_index) {
+      /* Find the port name of configuration chain head */
+      std::string src_port_name =
+        generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_INPUT);
+      net_src_module_id = parent_module;
+      net_src_instance_id = 0;
+      net_src_port_id =
+        module_manager.find_module_port(net_src_module_id, src_port_name);
+    } else {
+      /* Find the port name of previous memory module */
+      std::string src_port_name = generate_configuration_chain_tail_name();
+      net_src_module_id =
+        module_manager.configurable_children(parent_module)[mem_index - 1];
+      net_src_instance_id = module_manager.configurable_child_instances(
+        parent_module)[mem_index - 1];
+      net_src_port_id =
+        module_manager.find_module_port(net_src_module_id, src_port_name);
+    }
+
+    /* Get the pin id for source port */
+    BasicPort net_src_port =
+      module_manager.module_port(net_src_module_id, net_src_port_id);
+
+    /* Create a net for each pin */
+    for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
+      /* Find the net from which the source node is driving */
+      ModuleNetId net = module_manager.module_instance_port_net(
+        parent_module, net_src_module_id, net_src_instance_id, net_src_port_id,
+        net_src_port.pins()[pin_id]);
+      /* Remove the net including sources and sinks */
+      module_manager.clear_module_net_sinks(parent_module, net);
+    }
+  }
+
+  /* For the last memory module:
+   *    net source is the configuration chain tail of the previous memory module
+   *    net sink is the configuration chain tail of the primitive module
+   */
+  /* Find the port name of previous memory module */
+  std::string src_port_name = generate_configuration_chain_tail_name();
+  ModuleId net_src_module_id =
+    module_manager.configurable_children(parent_module).back();
+  size_t net_src_instance_id =
+    module_manager.configurable_child_instances(parent_module).back();
+  ModulePortId net_src_port_id =
+    module_manager.find_module_port(net_src_module_id, src_port_name);
+
+  /* Get the pin id for source port */
+  BasicPort net_src_port =
+    module_manager.module_port(net_src_module_id, net_src_port_id);
+
+  /* Create a net for each pin */
+  for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
+    /* Find the net from which the source node is driving */
+    ModuleNetId net = module_manager.module_instance_port_net(
+      parent_module, net_src_module_id, net_src_instance_id,
+      net_src_port_id, net_src_port.pins()[pin_id]);
+    /* Remove the net including sources and sinks */
+    module_manager.clear_module_net_sinks(parent_module, net);
+  }
+}
+
+/********************************************************************
+ * Remove the nets around the configurable children for a given module which
+ *should be in CMOS type
+ *******************************************************************/
+static int remove_submodule_nets_cmos_memory_config_bus(
+  ModuleManager& module_manager, const ModuleId& module_id,
+  const e_config_protocol_type& sram_orgz_type) {
+  switch (sram_orgz_type) {
+    case CONFIG_MEM_SCAN_CHAIN: {
+      remove_submodule_nets_cmos_memory_chain_config_bus(module_manager, module_id,
+                                                      sram_orgz_type);
+      break;
+    }
+    case CONFIG_MEM_STANDALONE:
+    case CONFIG_MEM_QL_MEMORY_BANK:
+      /* TODO:
+      add_module_nets_cmos_memory_bank_bl_config_bus(
+        module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
+      add_module_nets_cmos_memory_bank_wl_config_bus(
+        module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
+      add_module_nets_cmos_memory_bank_wl_config_bus(
+        module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR);
+       */
+      break;
+    case CONFIG_MEM_MEMORY_BANK:
+      /* TODO:
+      add_module_nets_cmos_flatten_memory_config_bus(
+        module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
+      add_module_nets_cmos_flatten_memory_config_bus(
+        module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
+       */
+      break;
+    case CONFIG_MEM_FRAME_BASED:
+      /* TODO:
+      add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib,
+                                                   parent_module);
+       */
+      break;
+    default:
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Invalid type of SRAM organization!\n");
+      exit(1);
+  }
+}
+
+/********************************************************************
+ * Remove the nets around the configurable children for a given module
+ *******************************************************************/
+static int remove_submodule_configurable_children_nets(
+  ModuleManager& module_manager, const ModuleId& module_id,
+  const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol) {
+  switch (circuit_lib.design_tech_type(config_protocol.memory_model())) {
+    case CIRCUIT_MODEL_DESIGN_CMOS:
+      remove_submodule_nets_cmos_memory_config_bus(module_manager, module_id,
+                                                config_protocol.type());
+      break;
+    case CIRCUIT_MODEL_DESIGN_RRAM:
+      /* TODO: */
+      break;
+    default:
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Invalid type of memory design technology!\n");
+      exit(1);
+  }
+}
+
+/********************************************************************
+ * Rebuild the nets(only sinks) around the configuration chain (ccff_head and
+ *ccff_tails)
+ *******************************************************************/
+static int rebuild_submodule_nets_cmos_memory_chain_config_bus(
+  ModuleManager& module_manager, const ModuleId& parent_module,
+  const e_config_protocol_type& sram_orgz_type) {
+  for (size_t mem_index = 0;
+       mem_index < module_manager.configurable_children(parent_module).size();
+       ++mem_index) {
+    ModuleId net_src_module_id;
+    size_t net_src_instance_id;
+    ModulePortId net_src_port_id;
+
+    ModuleId net_sink_module_id;
+    size_t net_sink_instance_id;
+    ModulePortId net_sink_port_id;
+
+    if (0 == mem_index) {
+      /* Find the port name of configuration chain head */
+      std::string src_port_name =
+        generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_INPUT);
+      net_src_module_id = parent_module;
+      net_src_instance_id = 0;
+      net_src_port_id =
+        module_manager.find_module_port(net_src_module_id, src_port_name);
+
+      /* Find the port name of next memory module */
+      std::string sink_port_name = generate_configuration_chain_head_name();
+      net_sink_module_id =
+        module_manager.configurable_children(parent_module)[mem_index];
+      net_sink_instance_id =
+        module_manager.configurable_child_instances(parent_module)[mem_index];
+      net_sink_port_id =
+        module_manager.find_module_port(net_sink_module_id, sink_port_name);
+    } else {
+      /* Find the port name of previous memory module */
+      std::string src_port_name = generate_configuration_chain_tail_name();
+      net_src_module_id =
+        module_manager.configurable_children(parent_module)[mem_index - 1];
+      net_src_instance_id = module_manager.configurable_child_instances(
+        parent_module)[mem_index - 1];
+      net_src_port_id =
+        module_manager.find_module_port(net_src_module_id, src_port_name);
+
+      /* Find the port name of next memory module */
+      std::string sink_port_name = generate_configuration_chain_head_name();
+      net_sink_module_id =
+        module_manager.configurable_children(parent_module)[mem_index];
+      net_sink_instance_id =
+        module_manager.configurable_child_instances(parent_module)[mem_index];
+      net_sink_port_id =
+        module_manager.find_module_port(net_sink_module_id, sink_port_name);
+    }
+
+    /* Get the pin id for source port */
+    BasicPort net_src_port =
+      module_manager.module_port(net_src_module_id, net_src_port_id);
+    /* Get the pin id for sink port */
+    BasicPort net_sink_port =
+      module_manager.module_port(net_sink_module_id, net_sink_port_id);
+    /* Port sizes of source and sink should match */
+    VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
+
+    /* Create a net for each pin */
+    for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
+      /* Create a net and add source and sink to it */
+      ModuleNetId net = create_module_source_pin_net(
+        module_manager, parent_module, net_src_module_id, net_src_instance_id,
+        net_src_port_id, net_src_port.pins()[pin_id]);
+      /* Add net sink */
+      module_manager.add_module_net_sink(parent_module, net, net_sink_module_id,
+                                         net_sink_instance_id, net_sink_port_id,
+                                         net_sink_port.pins()[pin_id]);
+    }
+  }
+
+  /* For the last memory module:
+   *    net source is the configuration chain tail of the previous memory module
+   *    net sink is the configuration chain tail of the primitive module
+   */
+  /* Find the port name of previous memory module */
+  std::string src_port_name = generate_configuration_chain_tail_name();
+  ModuleId net_src_module_id =
+    module_manager.configurable_children(parent_module).back();
+  size_t net_src_instance_id =
+    module_manager.configurable_child_instances(parent_module).back();
+  ModulePortId net_src_port_id =
+    module_manager.find_module_port(net_src_module_id, src_port_name);
+
+  /* Find the port name of next memory module */
+  std::string sink_port_name =
+    generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_OUTPUT);
+  ModuleId net_sink_module_id = parent_module;
+  size_t net_sink_instance_id = 0;
+  ModulePortId net_sink_port_id =
+    module_manager.find_module_port(net_sink_module_id, sink_port_name);
+
+  /* Get the pin id for source port */
+  BasicPort net_src_port =
+    module_manager.module_port(net_src_module_id, net_src_port_id);
+  /* Get the pin id for sink port */
+  BasicPort net_sink_port =
+    module_manager.module_port(net_sink_module_id, net_sink_port_id);
+  /* Port sizes of source and sink should match */
+  VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
+
+  /* Create a net for each pin */
+  for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
+    /* Create a net and add source and sink to it */
+    ModuleNetId net = create_module_source_pin_net(
+      module_manager, parent_module, net_src_module_id, net_src_instance_id,
+      net_src_port_id, net_src_port.pins()[pin_id]);
+    /* Add net sink */
+    module_manager.add_module_net_sink(parent_module, net, net_sink_module_id,
+                                       net_sink_instance_id, net_sink_port_id,
+                                       net_sink_port.pins()[pin_id]);
+  }
+}
+
+/********************************************************************
+ * Rebuild the nets around the configurable children for a given module which
+ *should be in CMOS type
+ *******************************************************************/
+static int rebuild_submodule_nets_cmos_memory_config_bus(
+  ModuleManager& module_manager, const ModuleId& module_id,
+  const e_config_protocol_type& sram_orgz_type) {
+  switch (sram_orgz_type) {
+    case CONFIG_MEM_SCAN_CHAIN: {
+      rebuild_submodule_nets_cmos_memory_chain_config_bus(
+        module_manager, module_id, sram_orgz_type);
+      break;
+    }
+    case CONFIG_MEM_STANDALONE:
+    case CONFIG_MEM_QL_MEMORY_BANK:
+      /* TODO:
+      add_module_nets_cmos_memory_bank_bl_config_bus(
+        module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
+      add_module_nets_cmos_memory_bank_wl_config_bus(
+        module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
+      add_module_nets_cmos_memory_bank_wl_config_bus(
+        module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WLR);
+       */
+      break;
+    case CONFIG_MEM_MEMORY_BANK:
+      /* TODO:
+      add_module_nets_cmos_flatten_memory_config_bus(
+        module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
+      add_module_nets_cmos_flatten_memory_config_bus(
+        module_manager, parent_module, sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
+       */
+      break;
+    case CONFIG_MEM_FRAME_BASED:
+      /* TODO:
+      add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib,
+                                                   parent_module);
+       */
+      break;
+    default:
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Invalid type of SRAM organization!\n");
+      exit(1);
+  }
+}
+
+/********************************************************************
+ * Rebuild the nets(only sinks) around the configurable children for a given
+ *module
+ *******************************************************************/
+static int rebuild_submodule_configurable_children_nets(
+  ModuleManager& module_manager, const ModuleId& module_id,
+  const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol) {
+  switch (circuit_lib.design_tech_type(config_protocol.memory_model())) {
+    case CIRCUIT_MODEL_DESIGN_CMOS:
+      rebuild_submodule_nets_cmos_memory_config_bus(module_manager, module_id,
+                                                 config_protocol.type());
+      break;
+    case CIRCUIT_MODEL_DESIGN_RRAM:
+      /* TODO: */
+      break;
+    default:
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Invalid type of memory design technology!\n");
+      exit(1);
+  }
+}
+
 /********************************************************************
  * Load and update the configurable children of a given module (not a top-level
  *module) Compare the configurable children list with fabric sub-keys.
@@ -2671,8 +2999,12 @@ static int load_and_update_submodule_memory_modules_from_fabric_key(
                                                 fabric_key, key_module_id)) {
     return CMD_EXEC_SUCCESS;
   }
-  /* TODO: Do not match, now remove all the nets for the configurable children
+  /* Do not match, now remove all the nets for the configurable children */
-   */
+  status = remove_submodule_configurable_children_nets(
+    module_manager, module_id, circuit_lib, config_protocol);
+  if (status == CMD_EXEC_FATAL_ERROR) {
+    return status;
+  }
   /* Overwrite the configurable children list */
   status = update_submodule_memory_modules_from_fabric_key(
     module_manager, module_id, circuit_lib, config_protocol, fabric_key,
@@ -2681,6 +3013,11 @@ static int load_and_update_submodule_memory_modules_from_fabric_key(
     return status;
   }
   /* TODO: Create the nets for the new list of configurable children */
+  status = rebuild_submodule_configurable_children_nets(
+    module_manager, module_id, circuit_lib, config_protocol);
+  if (status == CMD_EXEC_FATAL_ERROR) {
+    return status;
+  }
   return status;
 }