From d3109ee88b21a346139612f1aabcd8e047617e3a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 6 Jul 2023 21:53:22 -0700 Subject: [PATCH] [core] developing configurable children reloading from fabric key --- openfpga/src/fabric/build_top_module.cpp | 7 ++ openfpga/src/utils/module_manager_utils.cpp | 112 ++++++++++++++++++++ openfpga/src/utils/module_manager_utils.h | 6 ++ 3 files changed, 125 insertions(+) diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 395ca26f2..ff7fcac66 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -542,6 +542,13 @@ int build_top_module( if (CMD_EXEC_FATAL_ERROR == status) { return status; } + + /* Update the memory organization in sub module (non-top) */ + status = load_submodules_memory_modules_from_fabric_key( + module_manager, circuit_lib, config_protocol, fabric_key); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } } /* Shuffle the configurable children in a random sequence */ diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp index 90dbc2b41..5727f71de 100644 --- a/openfpga/src/utils/module_manager_utils.cpp +++ b/openfpga/src/utils/module_manager_utils.cpp @@ -8,6 +8,7 @@ #include /* Headers from vtrutil library */ +#include "command_exit_codes.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -2531,4 +2532,115 @@ void add_module_bus_nets( * *******************************************************************/ +/******************************************************************** + * Compare the configurable children list with a given list of fabric sub-keys + * Return true if exact naming-matches are found + * When searching for matching, we consider + * - alias is treated as No. 1 reference + * - the pair as No. 2 reference + *******************************************************************/ +static bool submodule_memory_modules_match_fabric_key( + ModuleManager& module_manager, const ModuleId& module_id, + const FabricKey& fabric_key, const FabricKeyModuleId& key_module_id) { + /* If the length does not match, conclusion is easy to be made */ + size_t len_module_memory = + module_manager.configurable_children(module_id).size(); + size_t len_fabric_sub_key = fabric_key.sub_keys(key_module_id).size(); + if (len_module_memory != len_fabric_sub_key) { + return false; + } + /* Now walk through the child one by one */ + for (size_t ikey = 0; ikey < len_module_memory; ++ikey) { + FabricSubKeyId key_id = fabric_key.sub_keys(key_module_id)[ikey]; + std::pair inst_info(ModuleId::INVALID(), 0); + /* Try to match the alias */ + if (!fabric_key.sub_key_alias(key_id).empty()) { + if (!fabric_key.sub_key_name(key_id).empty()) { + inst_info.first = + module_manager.find_module(fabric_key.sub_key_name(key_id)); + inst_info.second = module_manager.instance_id( + module_id, inst_info.first, fabric_key.sub_key_alias(key_id)); + } else { + inst_info = find_module_manager_instance_module_info( + module_manager, module_id, fabric_key.sub_key_alias(key_id)); + } + } else { + inst_info.first = + module_manager.find_module(fabric_key.sub_key_name(key_id)); + inst_info.second = fabric_key.sub_key_value(key_id); + } + if (inst_info.first != + module_manager.configurable_children(module_id)[ikey] || + inst_info.second != + module_manager.configurable_child_instances(module_id)[ikey]) { + return false; + } + } + return true; +} + +/******************************************************************** + * Load and update the configurable children of a given module (not a top-level + *module) Compare the configurable children list with fabric sub-keys. + * - If match, nothing should be done + * - If not match, + * - remove the nets related to configurable children + * - rebuild the configurable children list + * - add the nets related to configurable children + *******************************************************************/ +static int load_and_update_submodule_memory_modules_from_fabric_key( + ModuleManager& module_manager, const ModuleId& module_id, + const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, + const FabricKey& fabric_key, const FabricKeyModuleId& key_module_id) { + int status = CMD_EXEC_SUCCESS; + /* Compare the configurable children list */ + if (submodule_memory_modules_match_fabric_key(module_manager, module_id, + fabric_key, key_module_id)) { + return CMD_EXEC_SUCCESS; + } + /* TODO: Do not match, now remove all the nets for the configurable children + */ + /* TODO: Overwrite the configurable children list */ + /* TODO: Create the nets for the new list of configurable children */ + return status; +} + +/******************************************************************** + * Load and update the configurable children of a given list of modules (not a + *top-level module) + *******************************************************************/ +int load_submodules_memory_modules_from_fabric_key( + ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ConfigProtocol& config_protocol, const FabricKey& fabric_key) { + int status = CMD_EXEC_SUCCESS; + for (FabricKeyModuleId key_module_id : fabric_key.modules()) { + std::string module_name = fabric_key.module_name(key_module_id); + /* Ensure this is not a top module! */ + if (module_name == std::string(FPGA_TOP_MODULE_NAME)) { + VTR_LOG_ERROR( + "Expect a non-top-level name for the sub-module '%s' in fabric key!\n", + module_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + ModuleId module_id = module_manager.find_module(module_name); + if (module_id) { + /* This is a valid module, try to load and update */ + status = load_and_update_submodule_memory_modules_from_fabric_key( + module_manager, module_id, circuit_lib, config_protocol, fabric_key, + key_module_id); + if (status == CMD_EXEC_FATAL_ERROR) { + return status; + } + } else { + /* Not a valid module, report error */ + VTR_LOG_ERROR( + "The sub-module '%s' in fabric key is not a valid module in FPGA " + "fabric!\n", + module_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + } + return status; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h index bd4e43130..12061f014 100644 --- a/openfpga/src/utils/module_manager_utils.h +++ b/openfpga/src/utils/module_manager_utils.h @@ -20,7 +20,9 @@ /* Headers from readarchopenfpga library */ #include "circuit_library.h" #include "circuit_types.h" +#include "config_protocol.h" #include "decoder_library.h" +#include "fabric_key.h" #include "module_manager.h" #include "vpr_device_annotation.h" @@ -183,6 +185,10 @@ void add_module_bus_nets( const ModulePortId& src_module_port_id, const ModuleId& des_module_id, const size_t& des_instance_id, const ModulePortId& des_module_port_id); +int load_submodules_memory_modules_from_fabric_key( + ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const ConfigProtocol& config_protocol, const FabricKey& fabric_key); + } /* end namespace openfpga */ #endif