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Merge branch 'tileable_routing' into multimode_clb

This commit is contained in:
tangxifan 2019-06-26 15:00:39 -06:00
parent d2bd2be76b 57616361c2
commit d2ed82d14d
1 changed files with 10 additions and 8 deletions
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18
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
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@ -3871,8 +3871,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
if (TRUE == compact_routing_hierarchy) { if (TRUE == compact_routing_hierarchy) {
/* Create a snapshot on sram_orgz_info */ /* Create a snapshot on sram_orgz_info */
t_sram_orgz_info* stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info); t_sram_orgz_info* stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info);
/* Restore sram_orgz_info to the base */
copy_sram_orgz_info (cur_sram_orgz_info, stamped_sram_orgz_info);
DeviceCoordinator cb_range = device_rr_gsb.get_gsb_range(); DeviceCoordinator cb_range = device_rr_gsb.get_gsb_range();
@ -3881,6 +3879,16 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb); const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX); dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX);
} }
/* Y - channels [1...ny][0..nx]*/
for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY);
}
/* Restore sram_orgz_info to the base */
copy_sram_orgz_info (cur_sram_orgz_info, stamped_sram_orgz_info);
/* TODO: when we follow a tile organization, /* TODO: when we follow a tile organization,
* updating the conf bits should follow a tile organization: CLB, SB and CBX, CBY */ * updating the conf bits should follow a tile organization: CLB, SB and CBX, CBY */
for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { for (size_t ix = 0; ix < cb_range.get_x(); ++ix) {
@ -3890,12 +3898,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info,
} }
} }
/* Y - channels [1...ny][0..nx]*/
for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY);
}
for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { for (size_t ix = 0; ix < cb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { for (size_t iy = 0; iy < cb_range.get_y(); ++iy) {
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);