add check codes for mode bits annotation to pb_types and clean up utils source files

openfpga/src/base/annotate_pb_types.cpp

@@ -1019,6 +1019,8 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   VTR_LOG("Building annotation between physical pb_types and mode selection bits...\n");
   link_vpr_pb_type_to_mode_bits_explicit_annotation(vpr_device_ctx, openfpga_arch,
                                                     vpr_pb_type_annotation);
+  check_vpr_pb_type_mode_bits_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
+                                         const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
 
 } 
 

openfpga/src/base/check_pb_type_annotation.cpp

@@ -8,6 +8,7 @@
 #include "vtr_log.h"
 
 #include "pb_type_utils.h"
+#include "circuit_library_utils.h"
 #include "check_pb_type_annotation.h"
 
 /* begin namespace openfpga */
@@ -89,8 +90,8 @@ void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx,
   if (0 == num_err) {
     VTR_LOG("Check physical mode annotation for pb_types passed.\n");
   } else {
-    VTR_LOG("Check physical mode annotation for pb_types failed with %ld errors!\n",
+    VTR_LOG_ERROR("Check physical mode annotation for pb_types failed with %ld errors!\n",
-            num_err);
+                  num_err);
   }
 }
 
@@ -139,10 +140,7 @@ void rec_check_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
     return;
   }
 
-  /* Traverse all the modes
+  /* Traverse all the modes */
-   * - for pb_type children under a physical mode, we expect an physical mode 
-   * - for pb_type children under non-physical mode, we expect no physical mode 
-   */
   for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
     for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
       rec_check_vpr_physical_pb_type_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
@@ -173,8 +171,8 @@ void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
   if (0 == num_err) {
     VTR_LOG("Check physical pb_type annotation for pb_types passed.\n");
   } else {
-    VTR_LOG("Check physical pb_type annotation for pb_types failed with %ld errors!\n",
+    VTR_LOG_ERROR("Check physical pb_type annotation for pb_types failed with %ld errors!\n",
-            num_err);
+                  num_err);
   }
 }
 
@@ -274,4 +272,110 @@ void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_
   }
 }
 
+/********************************************************************
+ * This function will recursively traverse all the primitive pb_types 
+ * in the graph to ensure
+ *  - If a primitive pb_type has mode bits, it must have been linked to a physical pb_type
+ *    and the circuit model must have a port for mode selection. 
+ *    And the port size must match the length of mode bits
+ *******************************************************************/
+static 
+void rec_check_vpr_pb_type_mode_bits_annotation(t_pb_type* cur_pb_type,
+                                                const CircuitLibrary& circuit_lib,
+                                                const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                size_t& num_err) {
+  /* Primitive pb_type should always been binded to a physical pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    /* Find the physical pb_type
+     * If the physical pb_type has mode selection bits, this pb_type must have as well!
+     */
+    t_pb_type* physical_pb_type = vpr_pb_type_annotation.physical_pb_type(cur_pb_type);
+
+    if (nullptr == physical_pb_type) {
+      VTR_LOG_ERROR("Find a pb_type '%s' which has not been mapped to any physical pb_type!\n",
+                    cur_pb_type->name);
+      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+      num_err++;
+      return;
+    }
+
+    if (vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size() != vpr_pb_type_annotation.pb_type_mode_bits(physical_pb_type).size()) {
+      VTR_LOG_ERROR("Found different sizes of mode_bits for pb_type '%s' and its physical pb_type '%s'\n",
+                    cur_pb_type->name,
+                    physical_pb_type->name);
+      num_err++;
+      return;
+    }
+  
+    /* Try to find a mode selection port for the circuit model linked to the circuit model */
+    CircuitModelId circuit_model = vpr_pb_type_annotation.pb_type_circuit_model(physical_pb_type);
+    if (CircuitModelId::INVALID() == vpr_pb_type_annotation.pb_type_circuit_model(physical_pb_type)) {
+      VTR_LOG_ERROR("Found a physical pb_type '%s' missing circuit model binding!\n",
+                    physical_pb_type->name);
+      num_err++;
+      return; /* Invalid id already, further check is not applicable */
+    }
+    
+    if (0 == vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size()) {
+      /* No mode bits to be checked! */
+      return;
+    }
+    /* Search the ports of this circuit model and we must have a mode selection port */
+    std::vector<CircuitPortId> mode_select_ports = find_circuit_mode_select_sram_ports(circuit_lib, circuit_model);
+    size_t port_num_mode_bits = 0;
+    for (const CircuitPortId& mode_select_port : mode_select_ports) {
+      port_num_mode_bits += circuit_lib.port_size(mode_select_port);
+    }
+    if (port_num_mode_bits != vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size()) {
+      VTR_LOG_ERROR("Length of mode bits of pb_type '%s' does not match the size(%ld) of mode selection ports of circuit model '%s'!\n",
+                    cur_pb_type->name,
+                    port_num_mode_bits,
+                    circuit_lib.model_name(circuit_model).c_str());
+      num_err++;
+    }
+
+    return;
+  }
+
+  /* Traverse all the modes */
+  for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
+    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
+      rec_check_vpr_pb_type_mode_bits_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
+                                                 circuit_lib, vpr_pb_type_annotation,
+                                                 num_err);
+    }
+  }
+}
+
+/********************************************************************
+ * This function will check the mode_bits annotation for each pb_type 
+ *  - If a primitive pb_type has mode bits, it must have been linked to a physical pb_type
+ *  - If a primitive pb_type has mode bits, the circuit model must have 
+ *    a port for mode selection. And the port size must match the length of mode bits
+ *
+ * Note:
+ *  - This function should be run after circuit mode and mode bits annotation 
+ *    is completed 
+ *******************************************************************/
+void check_vpr_pb_type_mode_bits_annotation(const DeviceContext& vpr_device_ctx, 
+                                            const CircuitLibrary& circuit_lib,
+                                            const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  size_t num_err = 0;
+
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    /* Top pb_type should always has a physical mode! */
+    rec_check_vpr_pb_type_mode_bits_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation, num_err);
+  }
+  if (0 == num_err) {
+    VTR_LOG("Check pb_type annotation for mode selection bits passed.\n");
+  } else {
+    VTR_LOG_ERROR("Check physical pb_type annotation for mode selection bits failed with %ld errors!\n",
+                  num_err);
+  }
+}
+
 } /* end namespace openfpga */

openfpga/src/base/check_pb_type_annotation.h

@@ -25,6 +25,10 @@ void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_
                                                 const CircuitLibrary& circuit_lib,
                                                 const VprPbTypeAnnotation& vpr_pb_type_annotation);
 
+void check_vpr_pb_type_mode_bits_annotation(const DeviceContext& vpr_device_ctx, 
+                                            const CircuitLibrary& circuit_lib,
+                                            const VprPbTypeAnnotation& vpr_pb_type_annotation);
+
 } /* end namespace openfpga */
 
 #endif

openfpga/src/utils/circuit_library_utils.cpp

@@ -0,0 +1,229 @@
+/************************************************************************
+ * Function to perform fundamental operation for the circuit library 
+ * These functions are not universal methods for the CircuitLibrary class
+ * They are made to ease the development in some specific purposes
+ * Please classify such functions in this file
+ ***********************************************************************/
+#include <algorithm>
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "circuit_library_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Get the model id of a SRAM model that is used to configure 
+ * a circuit model
+ *******************************************************************/
+std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
+                                                     const CircuitModelId& circuit_model) {
+  /* SRAM model id is stored in the sram ports of a circuit model */
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM);
+  std::vector<CircuitModelId> sram_models;
+  
+  /* Create a list of sram models, but avoid duplicated model ids */
+  for (const auto& sram_port : sram_ports) {
+    CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port);
+    VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) );
+    if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) {
+      continue;  /* Already in the list, skip the addition */
+    }
+    /* Not in the list, add it */
+    sram_models.push_back(sram_model);
+  }
+  
+  return sram_models;
+}
+
+/********************************************************************
+ * Find regular (not mode select) sram ports of a circuit model
+ *******************************************************************/
+std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
+                                                           const CircuitModelId& circuit_model) {
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM, true);
+  std::vector<CircuitPortId> regular_sram_ports;
+
+  for (const auto& port : sram_ports) {
+    if (true == circuit_lib.port_is_mode_select(port)) {
+      continue;
+    }
+    regular_sram_ports.push_back(port);
+  }
+
+  return regular_sram_ports;
+}
+
+/********************************************************************
+ * Find mode select sram ports of a circuit model
+ *******************************************************************/
+std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
+                                                               const CircuitModelId& circuit_model) {
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM, true);
+  std::vector<CircuitPortId> mode_select_sram_ports;
+
+  for (const auto& port : sram_ports) {
+    if (false == circuit_lib.port_is_mode_select(port)) {
+      continue;
+    }
+    mode_select_sram_ports.push_back(port);
+  }
+
+  return mode_select_sram_ports;
+}
+
+
+/********************************************************************
+ * Find the number of shared configuration bits for a ReRAM circuit 
+ * TODO: this function is subjected to be changed due to ReRAM-based SRAM cell design!!!
+ *******************************************************************/
+static 
+size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                                const CircuitModelId& rram_model,
+                                                const e_config_protocol_type& config_protocol_type) {
+  size_t num_shared_config_bits = 0;
+
+  /* Branch on the organization of configuration protocol */ 
+  switch (config_protocol_type) {
+  case CONFIG_MEM_STANDALONE:
+  case CONFIG_MEM_SCAN_CHAIN:
+    break;
+  case CONFIG_MEM_MEMORY_BANK: {
+    /* Find BL/WL ports */
+    std::vector<CircuitPortId> blb_ports = circuit_lib.model_ports_by_type(rram_model, CIRCUIT_MODEL_PORT_BLB);
+    for (auto blb_port : blb_ports) {
+      num_shared_config_bits = std::max((int)num_shared_config_bits, (int)circuit_lib.port_size(blb_port) - 1);
+    }
+    break;
+  }    
+  default:
+    VTR_LOG_ERROR("Invalid type of configuration protocol!\n");
+    exit(1);
+  }
+
+  return num_shared_config_bits;
+}
+
+/********************************************************************
+ * A generic function to find the number of shared configuration bits 
+ * for circuit model
+ * It will return 0 for CMOS circuits 
+ * It will return the maximum shared configuration bits across ReRAM models
+ *
+ * Note: This function may give WRONG results when all the SRAM ports
+ * are not properly linked to its circuit models!
+ * So, it should be called after the SRAM linking is done!!!
+ *
+ * IMPORTANT: This function should NOT be used to find the number of shared configuration bits
+ * for a multiplexer, because the multiplexer size is determined during 
+ * the FPGA architecture generation (NOT during the XML parsing). 
+ *******************************************************************/
+size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                           const CircuitModelId& circuit_model,
+                                           const e_config_protocol_type& config_protocol_type) {
+  size_t num_shared_config_bits = 0;
+
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM);
+  for (auto sram_port : sram_ports) {
+    CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port);
+    VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) );
+
+    /* Depend on the design technolgy of SRAM model, the number of configuration bits will be different */
+    switch (circuit_lib.design_tech_type(sram_model)) {
+    case CIRCUIT_MODEL_DESIGN_CMOS: 
+      /* CMOS circuit do not need shared configuration bits */
+      break;
+    case CIRCUIT_MODEL_DESIGN_RRAM: 
+       /* RRAM circuit do need shared configuration bits, but it is subjected to the largest one among different SRAM models */
+       num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, config_protocol_type));
+       break;
+    default:
+      VTR_LOG_ERROR("Invalid design technology for SRAM circuit model!\n",
+                    circuit_lib.model_name(circuit_model).c_str());
+      exit(1);
+    }
+  } 
+
+  return num_shared_config_bits;
+}
+
+/********************************************************************
+ * A generic function to find the number of configuration bits 
+ * for circuit model
+ * It will sum up the sizes of all the sram ports 
+ * 
+ * IMPORTANT: This function should NOT be used to find the number of configuration bits
+ * for a multiplexer, because the multiplexer size is determined during 
+ * the FPGA architecture generation (NOT during the XML parsing). 
+ *******************************************************************/
+size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model) {
+  size_t num_config_bits = 0;
+
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM);
+  for (auto sram_port : sram_ports) {
+    num_config_bits += circuit_lib.port_size(sram_port); 
+  } 
+
+  return num_config_bits;
+}
+
+/********************************************************************
+ * A generic function to find all the global ports in a circuit library
+ * 
+ * IMPORTANT: This function will uniquify the global ports whose share 
+ * share the same name !!!
+ *******************************************************************/
+std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib) {
+  std::vector<CircuitPortId> global_ports;
+
+  for (auto port : circuit_lib.ports()) {
+    /* By pass non-global ports*/
+    if (false == circuit_lib.port_is_global(port)) {
+      continue;
+    }
+    /* Check if a same port with the same name has already been in the list */
+    bool add_to_list = true;
+    for (const auto& global_port : global_ports) {
+      if (0 == circuit_lib.port_prefix(port).compare(circuit_lib.port_prefix(global_port))) {
+        /* Same name, skip list update */
+        add_to_list = false;
+        break;
+      }
+    }
+    if (true == add_to_list) {
+      /* Add the global_port to the list */
+      global_ports.push_back(port);
+    }
+  } 
+
+  return global_ports;
+}
+
+/********************************************************************
+ * A generic function to find all the unique user-defined
+ * Verilog netlists in a circuit library
+ * Netlists with same names will be considered as one
+ *******************************************************************/
+std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib) {
+  std::vector<std::string> netlists;
+
+  for (const CircuitModelId& model : circuit_lib.models()) {
+    /* Skip empty netlist names */
+    if (true == circuit_lib.model_verilog_netlist(model).empty()) {
+      continue;
+    }
+    /* See if the netlist name is already in the list */
+    std::vector<std::string>::iterator it = std::find(netlists.begin(), netlists.end(), circuit_lib.model_verilog_netlist(model));
+    if (it == netlists.end()) {
+      netlists.push_back(circuit_lib.model_verilog_netlist(model));
+    }
+  }
+
+ return netlists;
+}
+
+} /* end namespace openfpga */

openfpga/src/utils/circuit_library_utils.h

@@ -0,0 +1,44 @@
+/********************************************************************
+ * Header file for circuit_library_utils.cpp
+ *******************************************************************/
+#ifndef CIRCUIT_LIBRARY_UTILS_H
+#define CIRCUIT_LIBRARY_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+
+#include <vector>
+#include "circuit_types.h"
+#include "circuit_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
+                                                     const CircuitModelId& circuit_model);
+
+std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
+                                                           const CircuitModelId& circuit_model);
+
+std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
+                                                               const CircuitModelId& circuit_model);
+
+size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                           const CircuitModelId& circuit_model,
+                                           const e_config_protocol_type& sram_orgz_type);
+
+size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model);
+
+std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib);
+
+std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif