From f2b665555043acd7008fb2f30bceecddce427654 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 20:19:44 -0700
Subject: [PATCH 01/48] [Test] Start porting to Github Actions with build test

---
 .github/workflows/build.yml             | 31 ++++++++++++++++
 .github/workflows/install_dependency.sh | 47 +++++++++++++++++++++++++
 2 files changed, 78 insertions(+)
 create mode 100644 .github/workflows/build.yml
 create mode 100644 .github/workflows/install_dependency.sh

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
new file mode 100644
index 000000000..dff1bf746
--- /dev/null
+++ b/.github/workflows/build.yml
@@ -0,0 +1,31 @@
+name: OpenFPGA CI
+
+# Run CI on
+# - each push
+# - each pull request
+# - scheduled weekly
+on:
+  push:
+  pull_request:
+  schedule:
+    - cron: '0 0 * * 0 ' # weekly
+
+# Multiple job to tests
+jobs:
+  # Test the compilation
+  build_gcc8:
+    runs-on: ubuntu-18.04
+
+    # Define the steps to run the build job
+    steps:
+      - name: Checkout OpenFPGA repo
+        uses: actions/checkout@v2
+
+      - name: Install dependency
+        run: source install_dependency.sh 
+
+      - name: Compile OpenFPGA
+        uses: nicledomaS/cmake_build_action@v1
+        with:
+          submodule_update: OFF
+          cmake_args: -DCMAKE_BUILD_TYPE=release;-DCMAKE_C_COMPILER=gcc-8;-DCMAKE_CXX_COMPILER=g++-8;
diff --git a/.github/workflows/install_dependency.sh b/.github/workflows/install_dependency.sh
new file mode 100644
index 000000000..5268bef23
--- /dev/null
+++ b/.github/workflows/install_dependency.sh
@@ -0,0 +1,47 @@
+# Install all the dependency for OpenFPGA in Ubuntu-18.04
+sudo apt-get update
+sudo apt-get install autoconf
+sudo apt-get install automake
+sudo apt-get install bash
+sudo apt-get install bison
+sudo apt-get install build-essential
+sudo apt-get install cmake
+sudo apt-get install ctags
+sudo apt-get install curl
+sudo apt-get install doxygen
+sudo apt-get install flex
+sudo apt-get install fontconfig
+sudo apt-get install gdb
+sudo apt-get install git
+sudo apt-get install gperf
+sudo apt-get install iverilog
+sudo apt-get install libcairo2-dev
+sudo apt-get install libevent-dev
+sudo apt-get install libfontconfig1-dev
+sudo apt-get install liblist-moreutils-perl
+sudo apt-get install libncurses5-dev
+sudo apt-get install libx11-dev
+sudo apt-get install libxft-dev
+sudo apt-get install libxml++2.6-dev
+sudo apt-get install perl
+sudo apt-get install python
+sudo apt-get install python-lxml
+sudo apt-get install texinfo
+sudo apt-get install time
+sudo apt-get install valgrind
+sudo apt-get install zip
+sudo apt-get install qt5-default
+sudo apt-get install clang-format-7
+# Add all the supported compilers
+sudo apt-get install g++-5
+sudo apt-get install gcc-5
+sudo apt-get install g++-6
+sudo apt-get install gcc-6
+sudo apt-get install g++-7
+sudo apt-get install gcc-7
+sudo apt-get install g++-8
+sudo apt-get install gcc-8
+sudo apt-get install g++-9
+sudo apt-get install gcc-9
+sudo apt-get install clang-6.0
+sudo apt-get install clang-8

From a95ddef90d9e4bf146226a9b2aea78c2f9bfbf5c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 20:22:59 -0700
Subject: [PATCH 02/48] [Test] Bug fix in calling scripts for Github Actions

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index dff1bf746..80b3b14e4 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -22,7 +22,7 @@ jobs:
         uses: actions/checkout@v2
 
       - name: Install dependency
-        run: source install_dependency.sh 
+        run: source ./.github/workflow/install_dependency.sh 
 
       - name: Compile OpenFPGA
         uses: nicledomaS/cmake_build_action@v1

From de44e8c9d1a76f54938e6873329e546aa2b0a484 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 20:24:18 -0700
Subject: [PATCH 03/48] [Test] Bug fix for github actions

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 80b3b14e4..aec44f64a 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -22,7 +22,7 @@ jobs:
         uses: actions/checkout@v2
 
       - name: Install dependency
-        run: source ./.github/workflow/install_dependency.sh 
+        run: source ./.github/workflows/install_dependency.sh 
 
       - name: Compile OpenFPGA
         uses: nicledomaS/cmake_build_action@v1

From 84c39315a5aaf5ed7bd958fb8f8f048c7dfb2647 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 20:40:05 -0700
Subject: [PATCH 04/48] [Test] Use example CMake build scripts from Github
 actions

---
 .github/workflows/build.yml | 30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index aec44f64a..296b98016 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -10,6 +10,11 @@ on:
   schedule:
     - cron: '0 0 * * 0 ' # weekly
 
+# Environment variables
+env:
+  # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
+  BUILD_TYPE: Release
+
 # Multiple job to tests
 jobs:
   # Test the compilation
@@ -24,8 +29,23 @@ jobs:
       - name: Install dependency
         run: source ./.github/workflows/install_dependency.sh 
 
-      - name: Compile OpenFPGA
-        uses: nicledomaS/cmake_build_action@v1
-        with:
-          submodule_update: OFF
-          cmake_args: -DCMAKE_BUILD_TYPE=release;-DCMAKE_C_COMPILER=gcc-8;-DCMAKE_CXX_COMPILER=g++-8;
+      - name: Create CMake build environment
+        # Some projects don't allow in-source building, so create a separate build directory
+        # We'll use this as our working directory for all subsequent commands
+        run: cmake -E make_directory ${{runner.workspace}}/build
+
+      - name: Configure CMake
+        # Use a bash shell so we can use the same syntax for environment variable
+        # access regardless of the host operating system
+        shell: bash
+        working-directory: ${{runner.workspace}}/build
+        # Note the current convention is to use the -S and -B options here to specify source 
+        # and build directories, but this is only available with CMake 3.13 and higher.  
+        # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
+        run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE
+
+      - name: Build
+        working-directory: ${{runner.workspace}}/build
+        shell: bash
+        # Execute the build.  You can specify a specific target with "--target <NAME>"
+        run: cmake --build . --config $BUILD_TYPE

From 7bd2622fd62ee4d02c42cfcfd1ce9aa78ac236ac Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 20:50:19 -0700
Subject: [PATCH 05/48] [Test] Try parallel build for Cmake in github actions

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 296b98016..d4f5602c8 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -48,4 +48,4 @@ jobs:
         working-directory: ${{runner.workspace}}/build
         shell: bash
         # Execute the build.  You can specify a specific target with "--target <NAME>"
-        run: cmake --build . --config $BUILD_TYPE
+        run: cmake --build . --config $BUILD_TYPE -j 8

From af21aa05223a2916953b77a8c48467176b754acb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 20:52:07 -0700
Subject: [PATCH 06/48] [Test]Try env variable for parallel cmake build

---
 .github/workflows/build.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index d4f5602c8..66a95a298 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -14,6 +14,7 @@ on:
 env:
   # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
   BUILD_TYPE: Release
+  MAKE_FLAGS: "-j8"
 
 # Multiple job to tests
 jobs:
@@ -48,4 +49,4 @@ jobs:
         working-directory: ${{runner.workspace}}/build
         shell: bash
         # Execute the build.  You can specify a specific target with "--target <NAME>"
-        run: cmake --build . --config $BUILD_TYPE -j 8
+        run: cmake --build . --config $BUILD_TYPE 

From 433c259d919b0cb28f410f8bdcba37455eccb444 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 22:28:17 -0700
Subject: [PATCH 07/48] [Test] Add ccache for compilation results to speed up
 CI

---
 .github/workflows/build.yml | 32 ++++++++++++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 66a95a298..56875bca7 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -19,8 +19,21 @@ env:
 # Multiple job to tests
 jobs:
   # Test the compilation
-  build_gcc8:
-    runs-on: ubuntu-18.04
+  build:
+    name: ${{ matrix.config.name }}
+    runs-on: ${{ matrix.config.os }}
+
+    # Branch on different OS and settings
+    strategy:
+      fail-fast: false
+      matrix:
+        config:
+        - {
+            name: "Build Compatibility: GCC-8 (Ubuntu 18.04)"
+            artifact: "OpenFPGA-ubuntu-18.04-gcc8-build.7z"
+            os: ubuntu-18.04
+            cc: "gcc-8", cxx: "g++-8"
+          }
 
     # Define the steps to run the build job
     steps:
@@ -30,6 +43,21 @@ jobs:
       - name: Install dependency
         run: source ./.github/workflows/install_dependency.sh 
 
+      - name: Prepare ccache timestamp
+          id: ccache_cache_timestamp
+          shell: cmake -P {0}
+          run: |
+          string(TIMESTAMP current_date "%Y-%m-%d-%H;%M;%S" UTC)
+          message("::set-output name=timestamp::${current_date}")
+      
+      - name: ccache cache files
+          uses: actions/cache@v1.1.0
+          with:
+          path: .ccache
+          key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
+          restore-keys: |
+            ${{ matrix.config.name }}-ccache-
+
       - name: Create CMake build environment
         # Some projects don't allow in-source building, so create a separate build directory
         # We'll use this as our working directory for all subsequent commands

From d3e2dee215f583245693edb4352bd52682f06fe8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 22:31:30 -0700
Subject: [PATCH 08/48] [Test] Bug fix in github action script

---
 .github/workflows/build.yml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 56875bca7..fda9fbc6d 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -29,9 +29,9 @@ jobs:
       matrix:
         config:
         - {
-            name: "Build Compatibility: GCC-8 (Ubuntu 18.04)"
-            artifact: "OpenFPGA-ubuntu-18.04-gcc8-build.7z"
-            os: ubuntu-18.04
+            name: "Build Compatibility: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
             cc: "gcc-8", cxx: "g++-8"
           }
 

From 6dbf22bc3d1ef5973c5bbc6bde33bbdbf58b1550 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 22:32:28 -0700
Subject: [PATCH 09/48] [Test] Add artifact upload

---
 .github/workflows/build.yml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index fda9fbc6d..18d8b6cbc 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -78,3 +78,9 @@ jobs:
         shell: bash
         # Execute the build.  You can specify a specific target with "--target <NAME>"
         run: cmake --build . --config $BUILD_TYPE 
+
+      - name: Upload
+        uses: actions/upload-artifact@v1
+        with:
+          path: ./${{ matrix.config.artifact }}
+          name: ${{ matrix.config.artifact }}

From 814aa49a5bb7e445500d25985eaadb5ad55c0a9d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 22:34:37 -0700
Subject: [PATCH 10/48] [Test] Bug fix in github Actions script

---
 .github/workflows/build.yml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 18d8b6cbc..ecab0aa2e 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -44,15 +44,15 @@ jobs:
         run: source ./.github/workflows/install_dependency.sh 
 
       - name: Prepare ccache timestamp
-          id: ccache_cache_timestamp
-          shell: cmake -P {0}
-          run: |
+        id: ccache_cache_timestamp
+        shell: cmake -P {0}
+        run: |
           string(TIMESTAMP current_date "%Y-%m-%d-%H;%M;%S" UTC)
           message("::set-output name=timestamp::${current_date}")
       
       - name: ccache cache files
-          uses: actions/cache@v1.1.0
-          with:
+        uses: actions/cache@v1.1.0
+        with:
           path: .ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
           restore-keys: |

From 703ba0b174124aed4d20632cb164220c6c074a4a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 22:46:20 -0700
Subject: [PATCH 11/48] [Test] Enable ccache in cmake execution

---
 .github/workflows/build.yml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index ecab0aa2e..4f89ffdc2 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -71,7 +71,10 @@ jobs:
         # Note the current convention is to use the -S and -B options here to specify source 
         # and build directories, but this is only available with CMake 3.13 and higher.  
         # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-        run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE
+        run: |
+          set(ENV{CC} ${{ matrix.config.cc }})
+          set(ENV{CXX} ${{ matrix.config.cxx }})
+          cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache
 
       - name: Build
         working-directory: ${{runner.workspace}}/build

From 4d2f6bc656c3dcf3fca8b80941bba5c9852e2c4a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 22:52:01 -0700
Subject: [PATCH 12/48] [Test] Bug fix

---
 .github/workflows/build.yml | 2 --
 1 file changed, 2 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 4f89ffdc2..7433f6e43 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -72,8 +72,6 @@ jobs:
         # and build directories, but this is only available with CMake 3.13 and higher.  
         # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
         run: |
-          set(ENV{CC} ${{ matrix.config.cc }})
-          set(ENV{CXX} ${{ matrix.config.cxx }})
           cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache
 
       - name: Build

From f417996b3634d827286c2226aacc30ad562e0f59 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 23 Nov 2020 22:57:19 -0700
Subject: [PATCH 13/48] [Test] Add ccache to dependency

---
 .github/workflows/install_dependency.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/install_dependency.sh b/.github/workflows/install_dependency.sh
index 5268bef23..0e663ef26 100644
--- a/.github/workflows/install_dependency.sh
+++ b/.github/workflows/install_dependency.sh
@@ -6,6 +6,7 @@ sudo apt-get install bash
 sudo apt-get install bison
 sudo apt-get install build-essential
 sudo apt-get install cmake
+sudo apt-get install ccache
 sudo apt-get install ctags
 sudo apt-get install curl
 sudo apt-get install doxygen

From 88bf523bc8ade95a98afb1b7f10fc716a93ad57e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 09:19:09 -0700
Subject: [PATCH 14/48] [Test] Remove artifact uploading; focus on testing
 ccache

---
 .github/workflows/build.yml | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 7433f6e43..df5a59a30 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -79,9 +79,3 @@ jobs:
         shell: bash
         # Execute the build.  You can specify a specific target with "--target <NAME>"
         run: cmake --build . --config $BUILD_TYPE 
-
-      - name: Upload
-        uses: actions/upload-artifact@v1
-        with:
-          path: ./${{ matrix.config.artifact }}
-          name: ${{ matrix.config.artifact }}

From 82954483b8a07689eb3d72a285343291c4e841d7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 09:29:11 -0700
Subject: [PATCH 15/48] [Test] Bug fix in using MAKEFLAGS

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index df5a59a30..8187200ac 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -14,7 +14,7 @@ on:
 env:
   # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
   BUILD_TYPE: Release
-  MAKE_FLAGS: "-j8"
+  MAKEFLAGS: "-j8"
 
 # Multiple job to tests
 jobs:

From 121f628f6b618988a90e4de42b70690261bb1c34 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 09:31:25 -0700
Subject: [PATCH 16/48] [Test] Add CXX and CC configuration

---
 .github/workflows/build.yml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 8187200ac..1df8eb133 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -72,6 +72,8 @@ jobs:
         # and build directories, but this is only available with CMake 3.13 and higher.  
         # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
         run: |
+          export CC = ${{ matrix.config.cc }}
+          export CXX = ${{ matrix.config.cxx }}
           cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache
 
       - name: Build

From c257abe864046258aa6aaa262e876ac8ca321ff0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 09:33:00 -0700
Subject: [PATCH 17/48] [Test] Add CMake and iVerilog version number output

---
 .github/workflows/build.yml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 1df8eb133..eb0f37a2f 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -43,6 +43,14 @@ jobs:
       - name: Install dependency
         run: source ./.github/workflows/install_dependency.sh 
 
+      - name: Checkout CMake version
+        run: cmake --version 
+
+      - name: Checkout iVerilog version
+        run: |
+          iverilog -V 
+          vvp -V 
+
       - name: Prepare ccache timestamp
         id: ccache_cache_timestamp
         shell: cmake -P {0}

From dc164a063664da95dc141273b75fc8c23931e11f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 09:38:18 -0700
Subject: [PATCH 18/48] [Test] Remove unnecssary space that break CI

---
 .github/workflows/build.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index eb0f37a2f..7326064b1 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -80,8 +80,8 @@ jobs:
         # and build directories, but this is only available with CMake 3.13 and higher.  
         # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
         run: |
-          export CC = ${{ matrix.config.cc }}
-          export CXX = ${{ matrix.config.cxx }}
+          export CC=${{ matrix.config.cc }}
+          export CXX=${{ matrix.config.cxx }}
           cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache
 
       - name: Build

From 3536f0baae63cd64d0646271aacb64bb27491dea Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 09:58:23 -0700
Subject: [PATCH 19/48] [Test] Adapt regression tests scripts for github
 actions

---
 .github/workflows/basic_reg_test.sh          | 107 +++++++++++++++++
 .github/workflows/fpga_bitstream_reg_test.sh |  21 ++++
 .github/workflows/fpga_sdc_reg_test.sh       |  11 ++
 .github/workflows/fpga_spice_reg_test.sh     |  11 ++
 .github/workflows/fpga_verilog_reg_test.sh   | 115 +++++++++++++++++++
 5 files changed, 265 insertions(+)
 create mode 100755 .github/workflows/basic_reg_test.sh
 create mode 100755 .github/workflows/fpga_bitstream_reg_test.sh
 create mode 100755 .github/workflows/fpga_sdc_reg_test.sh
 create mode 100755 .github/workflows/fpga_spice_reg_test.sh
 create mode 100755 .github/workflows/fpga_verilog_reg_test.sh

diff --git a/.github/workflows/basic_reg_test.sh b/.github/workflows/basic_reg_test.sh
new file mode 100755
index 000000000..c988c9a21
--- /dev/null
+++ b/.github/workflows/basic_reg_test.sh
@@ -0,0 +1,107 @@
+#!/bin/bash
+
+set -e
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "Basic regression tests";
+
+echo -e "Testing configuration chain of a K4N4 FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
+
+echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
+
+echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
+
+echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
+
+echo -e "Testing fixed device layout and routing channel width";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs
+
+echo -e "Testing fabric Verilog generation only";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs
+
+echo -e "Testing Verilog testbench generation only";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs
+
+echo -e "Testing separated Verilog fabric netlists and testbench locations";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
+
+echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs
+
+echo -e "Testing Secured FPGA fabrics";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
+
+
+echo -e "Testing K4 series FPGA";
+echo -e "Testing K4N4 with facturable LUTs";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
+echo -e "Testing K4N4 with hard adders";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
+echo -e "Testing K4N4 without local routing architecture";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
+echo -e "Testing K4N4 with block RAM";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
+echo -e "Testing K4N4 with multiple lengths of routing segments";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
+echo -e "Testing K4N4 with 32-bit fracturable multiplier";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
+echo -e "Testing K4N5 with pattern based local routing";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs
+
+echo -e "Testing different tile organizations";
+echo -e "Testing tiles with pins only on top and left sides";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs
+echo -e "Testing tiles with pins only on top and right sides";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs
+echo -e "Testing tiles with pins only on bottom and right sides";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs
+
+echo -e "Testing global port definition from tiles";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
diff --git a/.github/workflows/fpga_bitstream_reg_test.sh b/.github/workflows/fpga_bitstream_reg_test.sh
new file mode 100755
index 000000000..ce3693555
--- /dev/null
+++ b/.github/workflows/fpga_bitstream_reg_test.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+set -e
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "FPGA-Bitstream regression tests";
+
+echo -e "Testing bitstream generation for an auto-sized device";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
+
+
+echo -e "Testing bitstream generation for an 48x48 FPGA device";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs
+
+echo -e "Testing bitstream generation for an 96x96 FPGA device";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs
+
+echo -e "Testing loading architecture bitstream from an external file";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
diff --git a/.github/workflows/fpga_sdc_reg_test.sh b/.github/workflows/fpga_sdc_reg_test.sh
new file mode 100755
index 000000000..203106433
--- /dev/null
+++ b/.github/workflows/fpga_sdc_reg_test.sh
@@ -0,0 +1,11 @@
+#!/bin/bash
+
+set -e
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "FPGA-SDC regression tests";
+
+echo -e "Testing SDC generation with time units";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_sdc/sdc_time_unit --debug --show_thread_logs
diff --git a/.github/workflows/fpga_spice_reg_test.sh b/.github/workflows/fpga_spice_reg_test.sh
new file mode 100755
index 000000000..defe17ec9
--- /dev/null
+++ b/.github/workflows/fpga_spice_reg_test.sh
@@ -0,0 +1,11 @@
+#!/bin/bash
+
+set -e
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "FPGA-SPICE regression tests";
+
+echo -e "Testing FPGA-SPICE with netlist generation";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs
diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/.github/workflows/fpga_verilog_reg_test.sh
new file mode 100755
index 000000000..7fcf75b3e
--- /dev/null
+++ b/.github/workflows/fpga_verilog_reg_test.sh
@@ -0,0 +1,115 @@
+#!/bin/bash
+
+set -e
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "FPGA-Verilog Feature Tests";
+
+echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs
+
+echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
+
+echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
+
+echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
+
+echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with hard adder chain in CLBs ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with 16k block RAMs ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with embedded I/Os for an FPGA ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/embedded_io --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with SoC I/Os for an FPGA ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/soc_io --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with adder chain across an FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with shift register chain across an FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with scan chain across an FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with routing multiplexers without buffers";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with routing multiplexers with constant gnd input";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with routing multiplexers without constant inputs";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with behavioral description";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
+
+echo -e "Testing implicit Verilog generation";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with flatten routing modules";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with duplicated grid output pins";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with spy output pads";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
+
+
+echo -e "Testing Power-gating designs";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
+
+echo -e "Testing Depopulated crossbar in local routing";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
+
+echo -e "Testing Fully connected output crossbar in local routing";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
+
+echo -e "Testing through channels in tileable routing";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
+
+# Verify MCNC big20 benchmark suite with ModelSim 
+# Please make sure you have ModelSim installed in the environment
+# Otherwise, it will fail
+#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
+#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim 

From 0bb185f6a081f1965f6a30fff35e4d5f0c2dca2d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 10:16:24 -0700
Subject: [PATCH 20/48] [Test] Try to fix the problem on storing ccache results

---
 .github/workflows/build.yml | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 7326064b1..df0d38cfb 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -18,7 +18,7 @@ env:
 
 # Multiple job to tests
 jobs:
-  # Test the compilation
+  # Test the compilation compatibility
   build:
     name: ${{ matrix.config.name }}
     runs-on: ${{ matrix.config.os }}
@@ -57,19 +57,20 @@ jobs:
         run: |
           string(TIMESTAMP current_date "%Y-%m-%d-%H;%M;%S" UTC)
           message("::set-output name=timestamp::${current_date}")
-      
-      - name: ccache cache files
-        uses: actions/cache@v1.1.0
-        with:
-          path: .ccache
-          key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
-          restore-keys: |
-            ${{ matrix.config.name }}-ccache-
 
       - name: Create CMake build environment
         # Some projects don't allow in-source building, so create a separate build directory
         # We'll use this as our working directory for all subsequent commands
         run: cmake -E make_directory ${{runner.workspace}}/build
+      
+      - name: ccache cache files
+        uses: actions/cache@v1.1.0
+        working-directory: ${{runner.workspace}}/build
+        with:
+          path: .ccache
+          key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
+          restore-keys: |
+            ${{ matrix.config.name }}-ccache-
 
       - name: Configure CMake
         # Use a bash shell so we can use the same syntax for environment variable

From 0daa484134f6ce9382fc7e8c71f9dd166323c248 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 10:25:12 -0700
Subject: [PATCH 21/48] [Test] Remove wrong syntax about ccache

---
 .github/workflows/build.yml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index df0d38cfb..7cbcbc010 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -65,7 +65,6 @@ jobs:
       
       - name: ccache cache files
         uses: actions/cache@v1.1.0
-        working-directory: ${{runner.workspace}}/build
         with:
           path: .ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}

From 43564c584d020c58cf148b4d232ce38a2be8d1a3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 10:29:05 -0700
Subject: [PATCH 22/48] [Test] Add the matrix for compiler compatibility tests

---
 .github/workflows/build.yml | 42 +++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 7cbcbc010..19279b1bd 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -28,6 +28,27 @@ jobs:
       fail-fast: false
       matrix:
         config:
+        - {
+            name: "Build Compatibility: GCC-5 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-ubuntu-18.04-gcc5-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-5", cxx: "g++-5"
+          }
+
+        - {
+            name: "Build Compatibility: GCC-6 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-ubuntu-18.04-gcc6-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-6", cxx: "g++-6"
+          }
+
+        - {
+            name: "Build Compatibility: GCC-7 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-ubuntu-18.04-gcc7-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-7", cxx: "g++-7"
+          }
+
         - {
             name: "Build Compatibility: GCC-8 (Ubuntu 18.04)",
             artifact: "OpenFPGA-ubuntu-18.04-gcc8-build.7z",
@@ -35,6 +56,27 @@ jobs:
             cc: "gcc-8", cxx: "g++-8"
           }
 
+        - {
+            name: "Build Compatibility: GCC-9 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-ubuntu-18.04-gcc9-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-9", cxx: "g++-9"
+          }
+
+        - {
+            name: "Build Compatibility: Clang-6 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-ubuntu-18.04-clang6-build.7z",
+            os: ubuntu-18.04,
+            cc: "clang-6.0", cxx: "clang++-6.0"
+          }
+
+        - {
+            name: "Build Compatibility: Clang-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-ubuntu-18.04-clang8-build.7z",
+            os: ubuntu-18.04,
+            cc: "clang-8", cxx: "clang++-8"
+          }
+
     # Define the steps to run the build job
     steps:
       - name: Checkout OpenFPGA repo

From 6b9f236d818fdda440e221d5dc19582e68a75435 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 10:37:15 -0700
Subject: [PATCH 23/48] [Test] Specify paths to ccache files

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 19279b1bd..041263964 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -108,7 +108,7 @@ jobs:
       - name: ccache cache files
         uses: actions/cache@v1.1.0
         with:
-          path: .ccache
+          path: ${{runner.workspace}}/build/.ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
           restore-keys: |
             ${{ matrix.config.name }}-ccache-

From 04d84a12b5af626af3d88f17d21d9b55c49285c9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 10:43:17 -0700
Subject: [PATCH 24/48] [Test] Rename build tests

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 041263964..11f87e8d4 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -1,4 +1,4 @@
-name: OpenFPGA CI
+name: Build Compatibility Tests
 
 # Run CI on
 # - each push

From 5574c7b44067260d88233fa4ca2d6602a13cae92 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 11:03:31 -0700
Subject: [PATCH 25/48] [Test] Add regression tests to Github Actions

---
 .github/workflows/basic_test.yml | 159 +++++++++++++++++++++++++++++++
 1 file changed, 159 insertions(+)
 create mode 100644 .github/workflows/basic_test.yml

diff --git a/.github/workflows/basic_test.yml b/.github/workflows/basic_test.yml
new file mode 100644
index 000000000..4a42d12f4
--- /dev/null
+++ b/.github/workflows/basic_test.yml
@@ -0,0 +1,159 @@
+name: OpenFPGA Regression Tests
+
+# Run CI on
+# - each push
+# - each pull request
+# - scheduled weekly
+on:
+  push:
+  pull_request:
+  schedule:
+    - cron: '0 0 * * 0 ' # weekly
+
+# Environment variables
+env:
+  # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
+  BUILD_TYPE: Release
+  MAKEFLAGS: "-j8"
+
+# Multiple job to tests
+jobs:
+  # Test the functionality of OpenFPGA tools
+  build:
+    name: ${{ matrix.config.name }}
+    runs-on: ${{ matrix.config.os }}
+
+    # Branch on different OS and settings
+    strategy:
+      fail-fast: false
+      matrix:
+        config:
+        - {
+            name: "Basic Regression Tests: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-basic-tests-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-8", cxx: "g++-8"
+          }
+
+        - {
+            name: "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-fpga-verilog-tests-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-8", cxx: "g++-8"
+          }
+
+        - {
+            name: "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-fpga-bitstream-tests-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-8", cxx: "g++-8"
+          }
+
+        - {
+            name: "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-fpga-sdc-tests-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-8", cxx: "g++-8"
+          }
+
+        - {
+            name: "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-fpga-spice-tests-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-8", cxx: "g++-8"
+          }
+
+    # Define the steps to run the build job
+    steps:
+      - name: Checkout OpenFPGA repo
+        uses: actions/checkout@v2
+
+      - name: Install dependency
+        run: source ./.github/workflows/install_dependency.sh 
+
+      - name: Checkout CMake version
+        run: cmake --version 
+
+      - name: Checkout iVerilog version
+        run: |
+          iverilog -V 
+          vvp -V 
+
+      - name: Prepare ccache timestamp
+        id: ccache_cache_timestamp
+        shell: cmake -P {0}
+        run: |
+          string(TIMESTAMP current_date "%Y-%m-%d-%H;%M;%S" UTC)
+          message("::set-output name=timestamp::${current_date}")
+
+      - name: Create CMake build environment
+        # Some projects don't allow in-source building, so create a separate build directory
+        # We'll use this as our working directory for all subsequent commands
+        run: cmake -E make_directory ${{runner.workspace}}/build
+      
+      - name: ccache cache files
+        uses: actions/cache@v1.1.0
+        with:
+          path: ${{runner.workspace}}/build/.ccache
+          key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
+          restore-keys: |
+            ${{ matrix.config.name }}-ccache-
+
+      - name: Configure CMake
+        # Use a bash shell so we can use the same syntax for environment variable
+        # access regardless of the host operating system
+        shell: bash
+        working-directory: ${{runner.workspace}}/build
+        # Note the current convention is to use the -S and -B options here to specify source 
+        # and build directories, but this is only available with CMake 3.13 and higher.  
+        # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
+        run: |
+          export CC=${{ matrix.config.cc }}
+          export CXX=${{ matrix.config.cxx }}
+          cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache
+
+      - name: Build
+        working-directory: ${{runner.workspace}}/build
+        shell: bash
+        # Execute the build.  You can specify a specific target with "--target <NAME>"
+        run: cmake --build . --config $BUILD_TYPE 
+
+      - name: Basic Regression Tests
+        if: matrix.config.name == 'Basic Regression Tests: GCC-8 (Ubuntu 18.04)'
+        working-directory: ${{runner.workspace}}
+        shell: bash
+        # Execute the test. 
+        run: |
+          source basic_reg_test.sh
+        
+      - name: FPGA-Verilog Regression Tests
+        if: matrix.config.name == 'FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)'
+        working-directory: ${{runner.workspace}}
+        shell: bash
+        # Execute the test. 
+        run: |
+          source fpga_verilog_reg_test.sh
+
+      - name: FPGA-Bitstream Regression Tests
+        if: matrix.config.name == 'FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)'
+        working-directory: ${{runner.workspace}}
+        shell: bash
+        # Execute the test. 
+        run: |
+          source fpga_bitstream_reg_test.sh
+
+      - name: FPGA-SDC Regression Tests
+        if: matrix.config.name == 'FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)'
+        working-directory: ${{runner.workspace}}
+        shell: bash
+        # Execute the test. 
+        run: |
+          source fpga_sdc_reg_test.sh
+
+      - name: FPGA-SPICE Regression Tests
+        if: matrix.config.name == 'FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)'
+        working-directory: ${{runner.workspace}}
+        shell: bash
+        # Execute the test. 
+        run: |
+          source fpga_spice_reg_test.sh

From a6e55cbe94ea79d6d6d6f3a8bcaac30b756605fc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 11:07:10 -0700
Subject: [PATCH 26/48] [Test] Try to fix the syntax error in if clauses

---
 .github/workflows/basic_test.yml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/basic_test.yml b/.github/workflows/basic_test.yml
index 4a42d12f4..ad80dfb08 100644
--- a/.github/workflows/basic_test.yml
+++ b/.github/workflows/basic_test.yml
@@ -119,7 +119,7 @@ jobs:
         run: cmake --build . --config $BUILD_TYPE 
 
       - name: Basic Regression Tests
-        if: matrix.config.name == 'Basic Regression Tests: GCC-8 (Ubuntu 18.04)'
+        if: ${{ matrix.config.name }} == 'Basic Regression Tests: GCC-8 (Ubuntu 18.04)'
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -127,7 +127,7 @@ jobs:
           source basic_reg_test.sh
         
       - name: FPGA-Verilog Regression Tests
-        if: matrix.config.name == 'FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)'
+        if: ${{ matrix.config.name }} == 'FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)'
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -135,7 +135,7 @@ jobs:
           source fpga_verilog_reg_test.sh
 
       - name: FPGA-Bitstream Regression Tests
-        if: matrix.config.name == 'FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)'
+        if: ${{ matrix.config.name }} == 'FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)'
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -143,7 +143,7 @@ jobs:
           source fpga_bitstream_reg_test.sh
 
       - name: FPGA-SDC Regression Tests
-        if: matrix.config.name == 'FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)'
+        if: ${{ matrix.config.name }} == 'FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)'
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -151,7 +151,7 @@ jobs:
           source fpga_sdc_reg_test.sh
 
       - name: FPGA-SPICE Regression Tests
-        if: matrix.config.name == 'FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)'
+        if: ${{ matrix.config.name }} == 'FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)'
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 

From 6ee5fce61f1decda53503dfae52a77feac98a629 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 11:11:34 -0700
Subject: [PATCH 27/48] [Test] Fix if syntax errors

---
 .github/workflows/basic_test.yml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/basic_test.yml b/.github/workflows/basic_test.yml
index ad80dfb08..cacb3e9b5 100644
--- a/.github/workflows/basic_test.yml
+++ b/.github/workflows/basic_test.yml
@@ -119,7 +119,7 @@ jobs:
         run: cmake --build . --config $BUILD_TYPE 
 
       - name: Basic Regression Tests
-        if: ${{ matrix.config.name }} == 'Basic Regression Tests: GCC-8 (Ubuntu 18.04)'
+        if: ${{ matrix.config.name == 'Basic Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -127,7 +127,7 @@ jobs:
           source basic_reg_test.sh
         
       - name: FPGA-Verilog Regression Tests
-        if: ${{ matrix.config.name }} == 'FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)'
+        if: ${{ matrix.config.name == 'FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -135,7 +135,7 @@ jobs:
           source fpga_verilog_reg_test.sh
 
       - name: FPGA-Bitstream Regression Tests
-        if: ${{ matrix.config.name }} == 'FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)'
+        if: ${{ matrix.config.name == 'FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -143,7 +143,7 @@ jobs:
           source fpga_bitstream_reg_test.sh
 
       - name: FPGA-SDC Regression Tests
-        if: ${{ matrix.config.name }} == 'FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)'
+        if: ${{ matrix.config.name == 'FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -151,7 +151,7 @@ jobs:
           source fpga_sdc_reg_test.sh
 
       - name: FPGA-SPICE Regression Tests
-        if: ${{ matrix.config.name }} == 'FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)'
+        if: ${{ matrix.config.name == 'FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 

From abafeb01a8eb85dca7802f9ef5c9171636389280 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 11:20:40 -0700
Subject: [PATCH 28/48] [Test] Rename test yml and try to patch if errors

---
 .github/workflows/{basic_test.yml => reg_test.yml} | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
 rename .github/workflows/{basic_test.yml => reg_test.yml} (91%)

diff --git a/.github/workflows/basic_test.yml b/.github/workflows/reg_test.yml
similarity index 91%
rename from .github/workflows/basic_test.yml
rename to .github/workflows/reg_test.yml
index cacb3e9b5..0347cf343 100644
--- a/.github/workflows/basic_test.yml
+++ b/.github/workflows/reg_test.yml
@@ -19,7 +19,7 @@ env:
 # Multiple job to tests
 jobs:
   # Test the functionality of OpenFPGA tools
-  build:
+  reg_test:
     name: ${{ matrix.config.name }}
     runs-on: ${{ matrix.config.os }}
 
@@ -119,7 +119,7 @@ jobs:
         run: cmake --build . --config $BUILD_TYPE 
 
       - name: Basic Regression Tests
-        if: ${{ matrix.config.name == 'Basic Regression Tests: GCC-8 (Ubuntu 18.04)' }}
+        if: matrix.config.name == ${{'Basic Regression Tests: GCC-8 (Ubuntu 18.04)'}}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -127,7 +127,7 @@ jobs:
           source basic_reg_test.sh
         
       - name: FPGA-Verilog Regression Tests
-        if: ${{ matrix.config.name == 'FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)' }}
+        if: matrix.config.name == ${{'FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -135,7 +135,7 @@ jobs:
           source fpga_verilog_reg_test.sh
 
       - name: FPGA-Bitstream Regression Tests
-        if: ${{ matrix.config.name == 'FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)' }}
+        if: matrix.config.name == ${{'FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -143,7 +143,7 @@ jobs:
           source fpga_bitstream_reg_test.sh
 
       - name: FPGA-SDC Regression Tests
-        if: ${{ matrix.config.name == 'FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)' }}
+        if: matrix.config.name == ${{'FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -151,7 +151,7 @@ jobs:
           source fpga_sdc_reg_test.sh
 
       - name: FPGA-SPICE Regression Tests
-        if: ${{ matrix.config.name == 'FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)' }}
+        if: matrix.config.name == ${{'FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 

From 5b9c0886e93b887f67217dc4e647043ceedf9c3b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 11:23:54 -0700
Subject: [PATCH 29/48] [Test] Keep fixing the if syntax error

---
 .github/workflows/reg_test.yml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/reg_test.yml b/.github/workflows/reg_test.yml
index 0347cf343..d8de1387c 100644
--- a/.github/workflows/reg_test.yml
+++ b/.github/workflows/reg_test.yml
@@ -119,7 +119,7 @@ jobs:
         run: cmake --build . --config $BUILD_TYPE 
 
       - name: Basic Regression Tests
-        if: matrix.config.name == ${{'Basic Regression Tests: GCC-8 (Ubuntu 18.04)'}}
+        if: matrix.config.name STRQUAL ${{'Basic Regression Tests: GCC-8 (Ubuntu 18.04)'}}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -127,7 +127,7 @@ jobs:
           source basic_reg_test.sh
         
       - name: FPGA-Verilog Regression Tests
-        if: matrix.config.name == ${{'FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)' }}
+        if: matrix.config.name STRQUAL ${{'FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -135,7 +135,7 @@ jobs:
           source fpga_verilog_reg_test.sh
 
       - name: FPGA-Bitstream Regression Tests
-        if: matrix.config.name == ${{'FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)' }}
+        if: matrix.config.name STRQUAL ${{'FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -143,7 +143,7 @@ jobs:
           source fpga_bitstream_reg_test.sh
 
       - name: FPGA-SDC Regression Tests
-        if: matrix.config.name == ${{'FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)' }}
+        if: matrix.config.name STRQUAL ${{'FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
@@ -151,7 +151,7 @@ jobs:
           source fpga_sdc_reg_test.sh
 
       - name: FPGA-SPICE Regression Tests
-        if: matrix.config.name == ${{'FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)' }}
+        if: matrix.config.name STRQUAL ${{'FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 

From 87f2fa7a90989f9cdebe91e25f985dc2d1d820f5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 11:30:20 -0700
Subject: [PATCH 30/48] [Test] Use if in run blocks

---
 .github/workflows/reg_test.yml | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/.github/workflows/reg_test.yml b/.github/workflows/reg_test.yml
index d8de1387c..bfea1668e 100644
--- a/.github/workflows/reg_test.yml
+++ b/.github/workflows/reg_test.yml
@@ -119,41 +119,46 @@ jobs:
         run: cmake --build . --config $BUILD_TYPE 
 
       - name: Basic Regression Tests
-        if: matrix.config.name STRQUAL ${{'Basic Regression Tests: GCC-8 (Ubuntu 18.04)'}}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
         run: |
-          source basic_reg_test.sh
+          if ("${{matrix.config.name}}" STRQUAL "Basic Regression Tests: GCC-8 (Ubuntu 18.04)")
+            source basic_reg_test.sh
+          endif()
         
       - name: FPGA-Verilog Regression Tests
-        if: matrix.config.name STRQUAL ${{'FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
         run: |
-          source fpga_verilog_reg_test.sh
+          if ("${{matrix.config.name}}" STRQUAL "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)")
+            source fpga_verilog_reg_test.sh
+          endif()
 
       - name: FPGA-Bitstream Regression Tests
-        if: matrix.config.name STRQUAL ${{'FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
         run: |
-          source fpga_bitstream_reg_test.sh
+          if ("${{matrix.config.name}}" STRQUAL "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)")
+            source fpga_bitstream_reg_test.sh
+          endif()
 
       - name: FPGA-SDC Regression Tests
-        if: matrix.config.name STRQUAL ${{'FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
         run: |
-          source fpga_sdc_reg_test.sh
+          if ("${{matrix.config.name}}" STRQUAL "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)")
+            source fpga_sdc_reg_test.sh
+          endif()
 
       - name: FPGA-SPICE Regression Tests
-        if: matrix.config.name STRQUAL ${{'FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)' }}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
         run: |
-          source fpga_spice_reg_test.sh
+          if ("${{matrix.config.name}}" STRQUAL "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)")
+            source fpga_spice_reg_test.sh
+          endif()

From 68827a53b603497074e61a0842df70cdbc3e4ae0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 12:37:42 -0700
Subject: [PATCH 31/48] [Test] Bug fix in wrong paths to call regression test
 scripts

---
 .github/workflows/reg_test.yml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/reg_test.yml b/.github/workflows/reg_test.yml
index bfea1668e..feb09d086 100644
--- a/.github/workflows/reg_test.yml
+++ b/.github/workflows/reg_test.yml
@@ -124,7 +124,7 @@ jobs:
         # Execute the test. 
         run: |
           if ("${{matrix.config.name}}" STRQUAL "Basic Regression Tests: GCC-8 (Ubuntu 18.04)")
-            source basic_reg_test.sh
+            source ${{runner.workspace}}/.github/workflows/basic_reg_test.sh
           endif()
         
       - name: FPGA-Verilog Regression Tests
@@ -133,7 +133,7 @@ jobs:
         # Execute the test. 
         run: |
           if ("${{matrix.config.name}}" STRQUAL "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)")
-            source fpga_verilog_reg_test.sh
+            source ${{runner.workspace}}/.github/workflows/fpga_verilog_reg_test.sh
           endif()
 
       - name: FPGA-Bitstream Regression Tests
@@ -142,7 +142,7 @@ jobs:
         # Execute the test. 
         run: |
           if ("${{matrix.config.name}}" STRQUAL "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)")
-            source fpga_bitstream_reg_test.sh
+            source ${{runner.workspace}}/.github/workflows/fpga_bitstream_reg_test.sh
           endif()
 
       - name: FPGA-SDC Regression Tests
@@ -151,7 +151,7 @@ jobs:
         # Execute the test. 
         run: |
           if ("${{matrix.config.name}}" STRQUAL "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)")
-            source fpga_sdc_reg_test.sh
+            source ${{runner.workspace}}/.github/workflows/fpga_sdc_reg_test.sh
           endif()
 
       - name: FPGA-SPICE Regression Tests
@@ -160,5 +160,5 @@ jobs:
         # Execute the test. 
         run: |
           if ("${{matrix.config.name}}" STRQUAL "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)")
-            source fpga_spice_reg_test.sh
+            source ${{runner.workspace}}/.github/workflows/fpga_spice_reg_test.sh
           endif()

From 5210eae96072e9537218e9e0af0de26c4ab3dc8f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 13:41:47 -0700
Subject: [PATCH 32/48] [Test] Simplify syntax and avoid complex if logics

---
 .github/workflows/reg_test.yml | 57 +++++++---------------------------
 1 file changed, 12 insertions(+), 45 deletions(-)

diff --git a/.github/workflows/reg_test.yml b/.github/workflows/reg_test.yml
index feb09d086..4347a0c76 100644
--- a/.github/workflows/reg_test.yml
+++ b/.github/workflows/reg_test.yml
@@ -32,35 +32,40 @@ jobs:
             name: "Basic Regression Tests: GCC-8 (Ubuntu 18.04)",
             artifact: "OpenFPGA-basic-tests-ubuntu-18.04-gcc8-build.7z",
             os: ubuntu-18.04,
-            cc: "gcc-8", cxx: "g++-8"
+            cc: "gcc-8", cxx: "g++-8",
+            reg_script: "basic_reg_test.sh"
           }
 
         - {
             name: "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)",
             artifact: "OpenFPGA-fpga-verilog-tests-ubuntu-18.04-gcc8-build.7z",
             os: ubuntu-18.04,
-            cc: "gcc-8", cxx: "g++-8"
+            cc: "gcc-8", cxx: "g++-8",
+            reg_script: "fpga_verilog_reg_test.sh"
           }
 
         - {
             name: "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)",
             artifact: "OpenFPGA-fpga-bitstream-tests-ubuntu-18.04-gcc8-build.7z",
             os: ubuntu-18.04,
-            cc: "gcc-8", cxx: "g++-8"
+            cc: "gcc-8", cxx: "g++-8",
+            reg_script: "fpga_bitstream_reg_test.sh"
           }
 
         - {
             name: "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)",
             artifact: "OpenFPGA-fpga-sdc-tests-ubuntu-18.04-gcc8-build.7z",
             os: ubuntu-18.04,
-            cc: "gcc-8", cxx: "g++-8"
+            cc: "gcc-8", cxx: "g++-8",
+            reg_script: "fpga_sdc_reg_test.sh"
           }
 
         - {
             name: "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)",
             artifact: "OpenFPGA-fpga-spice-tests-ubuntu-18.04-gcc8-build.7z",
             os: ubuntu-18.04,
-            cc: "gcc-8", cxx: "g++-8"
+            cc: "gcc-8", cxx: "g++-8",
+            reg_script: "fpga_spice_reg_test.sh"
           }
 
     # Define the steps to run the build job
@@ -118,47 +123,9 @@ jobs:
         # Execute the build.  You can specify a specific target with "--target <NAME>"
         run: cmake --build . --config $BUILD_TYPE 
 
-      - name: Basic Regression Tests
+      - name: ${{matrix.config.name}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
         run: |
-          if ("${{matrix.config.name}}" STRQUAL "Basic Regression Tests: GCC-8 (Ubuntu 18.04)")
-            source ${{runner.workspace}}/.github/workflows/basic_reg_test.sh
-          endif()
-        
-      - name: FPGA-Verilog Regression Tests
-        working-directory: ${{runner.workspace}}
-        shell: bash
-        # Execute the test. 
-        run: |
-          if ("${{matrix.config.name}}" STRQUAL "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)")
-            source ${{runner.workspace}}/.github/workflows/fpga_verilog_reg_test.sh
-          endif()
-
-      - name: FPGA-Bitstream Regression Tests
-        working-directory: ${{runner.workspace}}
-        shell: bash
-        # Execute the test. 
-        run: |
-          if ("${{matrix.config.name}}" STRQUAL "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)")
-            source ${{runner.workspace}}/.github/workflows/fpga_bitstream_reg_test.sh
-          endif()
-
-      - name: FPGA-SDC Regression Tests
-        working-directory: ${{runner.workspace}}
-        shell: bash
-        # Execute the test. 
-        run: |
-          if ("${{matrix.config.name}}" STRQUAL "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)")
-            source ${{runner.workspace}}/.github/workflows/fpga_sdc_reg_test.sh
-          endif()
-
-      - name: FPGA-SPICE Regression Tests
-        working-directory: ${{runner.workspace}}
-        shell: bash
-        # Execute the test. 
-        run: |
-          if ("${{matrix.config.name}}" STRQUAL "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)")
-            source ${{runner.workspace}}/.github/workflows/fpga_spice_reg_test.sh
-          endif()
+          source ${{runner.workspace}}/.github/workflows/${{matrix.config.reg_script}}

From 03f18b776c03de3dbddb6bd4f23337ea6802a3c7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 13:44:14 -0700
Subject: [PATCH 33/48] [Test] typo fix

---
 .github/workflows/reg_test.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/reg_test.yml b/.github/workflows/reg_test.yml
index 4347a0c76..ab0980d4f 100644
--- a/.github/workflows/reg_test.yml
+++ b/.github/workflows/reg_test.yml
@@ -123,7 +123,7 @@ jobs:
         # Execute the build.  You can specify a specific target with "--target <NAME>"
         run: cmake --build . --config $BUILD_TYPE 
 
-      - name: ${{matrix.config.name}
+      - name: ${{matrix.config.name}}
         working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 

From 8bbbec37a3c678757d4d09a6776632d0fe09aefa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 13:56:01 -0700
Subject: [PATCH 34/48] [Doc] Add badges for Github Actions to frontpage README

---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index 5a8a9e960..44b237933 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,6 @@
 # Getting Started with OpenFPGA <img src="./docs/source/overview/figures/OpenFPGA_logo.png" width="200" align="right">
+![Build Compatibility Tests](https://github.com/LNIS-Projects/OpenFPGA/workflows/Build%20Compatibility%20Tests/badge.svg)
+![OpenFPGA Regression Tests](https://github.com/LNIS-Projects/OpenFPGA/workflows/OpenFPGA%20Regression%20Tests/badge.svg)
 [![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.com/LNIS-Projects/OpenFPGA)
 [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)
 

From 54db85c2f61959b7db3ceb08cc7fb95de1806757 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 14:27:40 -0700
Subject: [PATCH 35/48] [Test] Correct the path to test scripts

---
 .github/workflows/reg_test.yml | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/.github/workflows/reg_test.yml b/.github/workflows/reg_test.yml
index ab0980d4f..e77f55909 100644
--- a/.github/workflows/reg_test.yml
+++ b/.github/workflows/reg_test.yml
@@ -124,8 +124,6 @@ jobs:
         run: cmake --build . --config $BUILD_TYPE 
 
       - name: ${{matrix.config.name}}
-        working-directory: ${{runner.workspace}}
         shell: bash
         # Execute the test. 
-        run: |
-          source ${{runner.workspace}}/.github/workflows/${{matrix.config.reg_script}}
+        run: source ./.github/workflows/${{matrix.config.reg_script}}

From 955e49dca194d0a2694fc4d1a3608a0b36b5634e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 15:10:33 -0700
Subject: [PATCH 36/48] [Test] bug fix for ccache and enhance printing messages

---
 .github/workflows/build.yml    | 21 +++++++++++++++++++--
 .github/workflows/reg_test.yml | 18 +++++++++++++++++-
 2 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 11f87e8d4..f025a625b 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -108,11 +108,25 @@ jobs:
       - name: ccache cache files
         uses: actions/cache@v1.1.0
         with:
-          path: ${{runner.workspace}}/build/.ccache
+          path: .ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
           restore-keys: |
             ${{ matrix.config.name }}-ccache-
 
+      # Set up the paths for ccache and control the size under 400MB
+      - name: Configure ccache
+        shell: cmake -P {0}
+        run: |
+          file(TO_CMAKE_PATH "$ENV{GITHUB_WORKSPACE}" ccache_basedir)
+          set(ENV{CCACHE_BASEDIR} "${ccache_basedir}")
+          set(ENV{CCACHE_DIR} "${ccache_basedir}/.ccache")
+          set(ENV{CCACHE_COMPRESS} "true")
+          set(ENV{CCACHE_COMPRESSLEVEL} "6")
+          set(ENV{CCACHE_MAXSIZE} "400M")
+
+          execute_process(COMMAND ccache -p)
+          execute_process(COMMAND ccache -z)
+
       - name: Configure CMake
         # Use a bash shell so we can use the same syntax for environment variable
         # access regardless of the host operating system
@@ -130,4 +144,7 @@ jobs:
         working-directory: ${{runner.workspace}}/build
         shell: bash
         # Execute the build.  You can specify a specific target with "--target <NAME>"
-        run: cmake --build . --config $BUILD_TYPE 
+        # Check the cache size and see if it is over the limit
+        run: |
+          cmake --build . --config $BUILD_TYPE 
+          ccache -s
diff --git a/.github/workflows/reg_test.yml b/.github/workflows/reg_test.yml
index e77f55909..ea786178b 100644
--- a/.github/workflows/reg_test.yml
+++ b/.github/workflows/reg_test.yml
@@ -104,6 +104,20 @@ jobs:
           restore-keys: |
             ${{ matrix.config.name }}-ccache-
 
+      # Set up the paths for ccache and control the size under 400MB
+      - name: Configure ccache
+        shell: cmake -P {0}
+        run: |
+          file(TO_CMAKE_PATH "$ENV{GITHUB_WORKSPACE}" ccache_basedir)
+          set(ENV{CCACHE_BASEDIR} "${ccache_basedir}")
+          set(ENV{CCACHE_DIR} "${ccache_basedir}/.ccache")
+          set(ENV{CCACHE_COMPRESS} "true")
+          set(ENV{CCACHE_COMPRESSLEVEL} "6")
+          set(ENV{CCACHE_MAXSIZE} "400M")
+
+          execute_process(COMMAND ccache -p)
+          execute_process(COMMAND ccache -z)
+
       - name: Configure CMake
         # Use a bash shell so we can use the same syntax for environment variable
         # access regardless of the host operating system
@@ -121,7 +135,9 @@ jobs:
         working-directory: ${{runner.workspace}}/build
         shell: bash
         # Execute the build.  You can specify a specific target with "--target <NAME>"
-        run: cmake --build . --config $BUILD_TYPE 
+        run: |
+          cmake --build . --config $BUILD_TYPE 
+          ccache -s
 
       - name: ${{matrix.config.name}}
         shell: bash

From 27e68f1ea2d7d5009cdb4b4bdec2aac696f6e4e1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 15:20:38 -0700
Subject: [PATCH 37/48] [Test] Add check ccache size

---
 .github/workflows/build.yml | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index f025a625b..df1786757 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -144,7 +144,11 @@ jobs:
         working-directory: ${{runner.workspace}}/build
         shell: bash
         # Execute the build.  You can specify a specific target with "--target <NAME>"
-        # Check the cache size and see if it is over the limit
         run: |
           cmake --build . --config $BUILD_TYPE 
-          ccache -s
+
+      # Check the cache size and see if it is over the limit
+      - name: Check ccache size
+        shell: cmake -P {0}
+        run: |
+          execute_process(COMMAND ccache -s)

From ca593f23fc50a81df5be9c57e27f23bd15fd8d14 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 15:32:45 -0700
Subject: [PATCH 38/48] [Test] Merge reg test to build tests on Github Actions

---
 .github/workflows/build.yml    |  49 ++++++++++-
 .github/workflows/reg_test.yml | 145 ---------------------------------
 2 files changed, 48 insertions(+), 146 deletions(-)
 delete mode 100644 .github/workflows/reg_test.yml

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index df1786757..189ba90ac 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -1,4 +1,4 @@
-name: Build Compatibility Tests
+name: OpenFPGA Tests
 
 # Run CI on
 # - each push
@@ -77,6 +77,47 @@ jobs:
             cc: "clang-8", cxx: "clang++-8"
           }
 
+        - {
+            name: "Basic Regression Tests: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-basic-tests-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-8", cxx: "g++-8",
+            reg_script: "basic_reg_test.sh"
+          }
+
+        - {
+            name: "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-fpga-verilog-tests-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-8", cxx: "g++-8",
+            reg_script: "fpga_verilog_reg_test.sh"
+          }
+
+        - {
+            name: "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-fpga-bitstream-tests-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-8", cxx: "g++-8",
+            reg_script: "fpga_bitstream_reg_test.sh"
+          }
+
+        - {
+            name: "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-fpga-sdc-tests-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-8", cxx: "g++-8",
+            reg_script: "fpga_sdc_reg_test.sh"
+          }
+
+        - {
+            name: "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)",
+            artifact: "OpenFPGA-fpga-spice-tests-ubuntu-18.04-gcc8-build.7z",
+            os: ubuntu-18.04,
+            cc: "gcc-8", cxx: "g++-8",
+            reg_script: "fpga_spice_reg_test.sh"
+          }
+
+
     # Define the steps to run the build job
     steps:
       - name: Checkout OpenFPGA repo
@@ -152,3 +193,9 @@ jobs:
         shell: cmake -P {0}
         run: |
           execute_process(COMMAND ccache -s)
+
+      - name: ${{matrix.config.name}}
+        if: contains(matrix.config.name, 'Regression Test')
+        shell: bash
+        # Execute the test. 
+        run: source ./.github/workflows/${{matrix.config.reg_script}}
diff --git a/.github/workflows/reg_test.yml b/.github/workflows/reg_test.yml
deleted file mode 100644
index ea786178b..000000000
--- a/.github/workflows/reg_test.yml
+++ /dev/null
@@ -1,145 +0,0 @@
-name: OpenFPGA Regression Tests
-
-# Run CI on
-# - each push
-# - each pull request
-# - scheduled weekly
-on:
-  push:
-  pull_request:
-  schedule:
-    - cron: '0 0 * * 0 ' # weekly
-
-# Environment variables
-env:
-  # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
-  BUILD_TYPE: Release
-  MAKEFLAGS: "-j8"
-
-# Multiple job to tests
-jobs:
-  # Test the functionality of OpenFPGA tools
-  reg_test:
-    name: ${{ matrix.config.name }}
-    runs-on: ${{ matrix.config.os }}
-
-    # Branch on different OS and settings
-    strategy:
-      fail-fast: false
-      matrix:
-        config:
-        - {
-            name: "Basic Regression Tests: GCC-8 (Ubuntu 18.04)",
-            artifact: "OpenFPGA-basic-tests-ubuntu-18.04-gcc8-build.7z",
-            os: ubuntu-18.04,
-            cc: "gcc-8", cxx: "g++-8",
-            reg_script: "basic_reg_test.sh"
-          }
-
-        - {
-            name: "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)",
-            artifact: "OpenFPGA-fpga-verilog-tests-ubuntu-18.04-gcc8-build.7z",
-            os: ubuntu-18.04,
-            cc: "gcc-8", cxx: "g++-8",
-            reg_script: "fpga_verilog_reg_test.sh"
-          }
-
-        - {
-            name: "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)",
-            artifact: "OpenFPGA-fpga-bitstream-tests-ubuntu-18.04-gcc8-build.7z",
-            os: ubuntu-18.04,
-            cc: "gcc-8", cxx: "g++-8",
-            reg_script: "fpga_bitstream_reg_test.sh"
-          }
-
-        - {
-            name: "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)",
-            artifact: "OpenFPGA-fpga-sdc-tests-ubuntu-18.04-gcc8-build.7z",
-            os: ubuntu-18.04,
-            cc: "gcc-8", cxx: "g++-8",
-            reg_script: "fpga_sdc_reg_test.sh"
-          }
-
-        - {
-            name: "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)",
-            artifact: "OpenFPGA-fpga-spice-tests-ubuntu-18.04-gcc8-build.7z",
-            os: ubuntu-18.04,
-            cc: "gcc-8", cxx: "g++-8",
-            reg_script: "fpga_spice_reg_test.sh"
-          }
-
-    # Define the steps to run the build job
-    steps:
-      - name: Checkout OpenFPGA repo
-        uses: actions/checkout@v2
-
-      - name: Install dependency
-        run: source ./.github/workflows/install_dependency.sh 
-
-      - name: Checkout CMake version
-        run: cmake --version 
-
-      - name: Checkout iVerilog version
-        run: |
-          iverilog -V 
-          vvp -V 
-
-      - name: Prepare ccache timestamp
-        id: ccache_cache_timestamp
-        shell: cmake -P {0}
-        run: |
-          string(TIMESTAMP current_date "%Y-%m-%d-%H;%M;%S" UTC)
-          message("::set-output name=timestamp::${current_date}")
-
-      - name: Create CMake build environment
-        # Some projects don't allow in-source building, so create a separate build directory
-        # We'll use this as our working directory for all subsequent commands
-        run: cmake -E make_directory ${{runner.workspace}}/build
-      
-      - name: ccache cache files
-        uses: actions/cache@v1.1.0
-        with:
-          path: ${{runner.workspace}}/build/.ccache
-          key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
-          restore-keys: |
-            ${{ matrix.config.name }}-ccache-
-
-      # Set up the paths for ccache and control the size under 400MB
-      - name: Configure ccache
-        shell: cmake -P {0}
-        run: |
-          file(TO_CMAKE_PATH "$ENV{GITHUB_WORKSPACE}" ccache_basedir)
-          set(ENV{CCACHE_BASEDIR} "${ccache_basedir}")
-          set(ENV{CCACHE_DIR} "${ccache_basedir}/.ccache")
-          set(ENV{CCACHE_COMPRESS} "true")
-          set(ENV{CCACHE_COMPRESSLEVEL} "6")
-          set(ENV{CCACHE_MAXSIZE} "400M")
-
-          execute_process(COMMAND ccache -p)
-          execute_process(COMMAND ccache -z)
-
-      - name: Configure CMake
-        # Use a bash shell so we can use the same syntax for environment variable
-        # access regardless of the host operating system
-        shell: bash
-        working-directory: ${{runner.workspace}}/build
-        # Note the current convention is to use the -S and -B options here to specify source 
-        # and build directories, but this is only available with CMake 3.13 and higher.  
-        # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-        run: |
-          export CC=${{ matrix.config.cc }}
-          export CXX=${{ matrix.config.cxx }}
-          cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache
-
-      - name: Build
-        working-directory: ${{runner.workspace}}/build
-        shell: bash
-        # Execute the build.  You can specify a specific target with "--target <NAME>"
-        run: |
-          cmake --build . --config $BUILD_TYPE 
-          ccache -s
-
-      - name: ${{matrix.config.name}}
-        shell: bash
-        # Execute the test. 
-        run: source ./.github/workflows/${{matrix.config.reg_script}}

From ab3c41715e11a6246a5ce246ea4e4aaf258baf70 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 15:44:16 -0700
Subject: [PATCH 39/48] [Doc] Update badges for the github actions

---
 README.md | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 44b237933..c5e81b04b 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,5 @@
 # Getting Started with OpenFPGA <img src="./docs/source/overview/figures/OpenFPGA_logo.png" width="200" align="right">
-![Build Compatibility Tests](https://github.com/LNIS-Projects/OpenFPGA/workflows/Build%20Compatibility%20Tests/badge.svg)
-![OpenFPGA Regression Tests](https://github.com/LNIS-Projects/OpenFPGA/workflows/OpenFPGA%20Regression%20Tests/badge.svg)
+![Github Actions Status](https://github.com/LNIS-Projects/OpenFPGA/workflows/OpenFPGA%20Tests/badge.svg)
 [![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.com/LNIS-Projects/OpenFPGA)
 [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)
 

From cba07b60200736ad2d557acf5073987532afe5e0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 15:58:09 -0700
Subject: [PATCH 40/48] [Test] Now travis and github actions share the common
 regression test scripts

---
 .travis/basic_reg_test.sh          | 104 +--------------------------
 .travis/fpga_bitstream_reg_test.sh |  18 +----
 .travis/fpga_sdc_reg_test.sh       |   8 +--
 .travis/fpga_spice_reg_test.sh     |   8 +--
 .travis/fpga_verilog_reg_test.sh   | 112 +----------------------------
 5 files changed, 5 insertions(+), 245 deletions(-)

diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh
index 207953644..c077b66fd 100755
--- a/.travis/basic_reg_test.sh
+++ b/.travis/basic_reg_test.sh
@@ -5,108 +5,6 @@ set -e
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd ${TRAVIS_BUILD_DIR}
 
-###############################################
-# OpenFPGA Shell with VPR8
-##############################################
-echo -e "Basic regression tests";
-
-echo -e "Testing configuration chain of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
-
-echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
-
-echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
-
-echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
-
-echo -e "Testing fixed device layout and routing channel width";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs
-
-echo -e "Testing fabric Verilog generation only";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs
-
-echo -e "Testing Verilog testbench generation only";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs
-
-echo -e "Testing separated Verilog fabric netlists and testbench locations";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
-
-echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs
-
-echo -e "Testing Secured FPGA fabrics";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
-
-
-echo -e "Testing K4 series FPGA";
-echo -e "Testing K4N4 with facturable LUTs";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
-echo -e "Testing K4N4 with hard adders";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
-echo -e "Testing K4N4 without local routing architecture";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
-echo -e "Testing K4N4 with block RAM";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
-echo -e "Testing K4N4 with multiple lengths of routing segments";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
-echo -e "Testing K4N4 with 32-bit fracturable multiplier";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
-echo -e "Testing K4N5 with pattern based local routing";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs
-
-echo -e "Testing different tile organizations";
-echo -e "Testing tiles with pins only on top and left sides";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs
-echo -e "Testing tiles with pins only on top and right sides";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs
-echo -e "Testing tiles with pins only on bottom and right sides";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs
-
-echo -e "Testing global port definition from tiles";
-python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
+source .github/workflows/basic_reg_test.sh
 
 end_section "OpenFPGA.TaskTun"
diff --git a/.travis/fpga_bitstream_reg_test.sh b/.travis/fpga_bitstream_reg_test.sh
index 8b9b6c0f4..4d7c27ed6 100755
--- a/.travis/fpga_bitstream_reg_test.sh
+++ b/.travis/fpga_bitstream_reg_test.sh
@@ -5,22 +5,6 @@ set -e
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd ${TRAVIS_BUILD_DIR}
 
-###############################################
-# OpenFPGA Shell with VPR8
-##############################################
-echo -e "FPGA-Bitstream regression tests";
-
-echo -e "Testing bitstream generation for an auto-sized device";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
-
-
-echo -e "Testing bitstream generation for an 48x48 FPGA device";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs
-
-echo -e "Testing bitstream generation for an 96x96 FPGA device";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs
-
-echo -e "Testing loading architecture bitstream from an external file";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
+source .github/workflows/fpga_bitstream_reg_test.sh
 
 end_section "OpenFPGA.TaskTun"
diff --git a/.travis/fpga_sdc_reg_test.sh b/.travis/fpga_sdc_reg_test.sh
index 70dd34809..bd0e5ae1f 100755
--- a/.travis/fpga_sdc_reg_test.sh
+++ b/.travis/fpga_sdc_reg_test.sh
@@ -5,12 +5,6 @@ set -e
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd ${TRAVIS_BUILD_DIR}
 
-###############################################
-# OpenFPGA Shell with VPR8
-##############################################
-echo -e "FPGA-SDC regression tests";
-
-echo -e "Testing SDC generation with time units";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_sdc/sdc_time_unit --debug --show_thread_logs
+source .github/workflows/fpga_sdc_reg_test.sh
 
 end_section "OpenFPGA.TaskTun"
diff --git a/.travis/fpga_spice_reg_test.sh b/.travis/fpga_spice_reg_test.sh
index 8856d3ec8..bb2a9afe6 100755
--- a/.travis/fpga_spice_reg_test.sh
+++ b/.travis/fpga_spice_reg_test.sh
@@ -5,12 +5,6 @@ set -e
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd ${TRAVIS_BUILD_DIR}
 
-###############################################
-# OpenFPGA Shell with VPR8
-##############################################
-echo -e "FPGA-SPICE regression tests";
-
-echo -e "Testing FPGA-SPICE with netlist generation";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs
+source .github/workflows/fpga_spice_reg_test.sh
 
 end_section "OpenFPGA.TaskTun"
diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index f06ae29fe..34a5c9d55 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -5,116 +5,6 @@ set -e
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd ${TRAVIS_BUILD_DIR}
 
-###############################################
-# OpenFPGA Shell with VPR8
-##############################################
-echo -e "FPGA-Verilog Feature Tests";
-
-echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs
-
-echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
-
-echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
-
-echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
-
-echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with hard adder chain in CLBs ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with 16k block RAMs ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with embedded I/Os for an FPGA ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/embedded_io --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with SoC I/Os for an FPGA ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/soc_io --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with adder chain across an FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with shift register chain across an FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with scan chain across an FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with routing multiplexers without buffers";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with routing multiplexers with constant gnd input";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with routing multiplexers without constant inputs";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with behavioral description";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
-
-echo -e "Testing implicit Verilog generation";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with flatten routing modules";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with duplicated grid output pins";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with spy output pads";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
-
-
-echo -e "Testing Power-gating designs";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
-
-echo -e "Testing Depopulated crossbar in local routing";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
-
-echo -e "Testing Fully connected output crossbar in local routing";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
-
-echo -e "Testing through channels in tileable routing";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
-
-# Verify MCNC big20 benchmark suite with ModelSim 
-# Please make sure you have ModelSim installed in the environment
-# Otherwise, it will fail
-#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
-#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim 
+source .github/workflows/fpga_verilog_reg_test.sh
 
 end_section "OpenFPGA.TaskTun"

From c7d288c0438b4f3fa555974a26c4c49267730112 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 16:50:29 -0700
Subject: [PATCH 41/48] [Test] Try to new cache action version to see if
 problem is solved

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 189ba90ac..c6889477c 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -147,7 +147,7 @@ jobs:
         run: cmake -E make_directory ${{runner.workspace}}/build
       
       - name: ccache cache files
-        uses: actions/cache@v1.1.0
+        uses: actions/cache@v2
         with:
           path: .ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}

From df317271fd076ca89a76cdc827ff38f75d99faf8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 16:54:55 -0700
Subject: [PATCH 42/48] [Test] Try to check if .ccache is in the build
 directory

---
 .github/workflows/build.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index c6889477c..ba058cda0 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -149,7 +149,7 @@ jobs:
       - name: ccache cache files
         uses: actions/cache@v2
         with:
-          path: .ccache
+          path: ${{runner.workspace}}/build/.ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
           restore-keys: |
             ${{ matrix.config.name }}-ccache-
@@ -190,6 +190,7 @@ jobs:
 
       # Check the cache size and see if it is over the limit
       - name: Check ccache size
+        working-directory: ${{runner.workspace}}/build
         shell: cmake -P {0}
         run: |
           execute_process(COMMAND ccache -s)

From 0af1c0468e947ce44dad6368a30c2fc65bea5a31 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 17:41:27 -0700
Subject: [PATCH 43/48] [Test] Spot cache file and try to use it

---
 .github/workflows/build.yml | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index ba058cda0..75861b134 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -149,7 +149,7 @@ jobs:
       - name: ccache cache files
         uses: actions/cache@v2
         with:
-          path: ${{runner.workspace}}/build/.ccache
+          path: ~/.ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
           restore-keys: |
             ${{ matrix.config.name }}-ccache-
@@ -190,7 +190,6 @@ jobs:
 
       # Check the cache size and see if it is over the limit
       - name: Check ccache size
-        working-directory: ${{runner.workspace}}/build
         shell: cmake -P {0}
         run: |
           execute_process(COMMAND ccache -s)

From 6b757e2dca090ed49d4539d1ac391c55f463f762 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 17:50:22 -0700
Subject: [PATCH 44/48] [Test] Bug fix in ccache path

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 75861b134..0075931e6 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -149,7 +149,7 @@ jobs:
       - name: ccache cache files
         uses: actions/cache@v2
         with:
-          path: ~/.ccache
+          path: ${{runner.workspace}}/.ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
           restore-keys: |
             ${{ matrix.config.name }}-ccache-

From 9f956502b76060dab5fa3d8213c9cd470b78a188 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 17:56:08 -0700
Subject: [PATCH 45/48] [Test] keep fixing the path to ccache file

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 0075931e6..2161ce538 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -149,7 +149,7 @@ jobs:
       - name: ccache cache files
         uses: actions/cache@v2
         with:
-          path: ${{runner.workspace}}/.ccache
+          path: ${GITHUB_WORKSPACE}/.ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
           restore-keys: |
             ${{ matrix.config.name }}-ccache-

From 91709abe803ea19eb53dd0d86599ed9988192d69 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 18:00:59 -0700
Subject: [PATCH 46/48] [Test] Try to get the correct path to github workspace

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 2161ce538..bb280b890 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -149,7 +149,7 @@ jobs:
       - name: ccache cache files
         uses: actions/cache@v2
         with:
-          path: ${GITHUB_WORKSPACE}/.ccache
+          path: $ENV{GITHUB_WORKSPACE}/.ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
           restore-keys: |
             ${{ matrix.config.name }}-ccache-

From df98c83d33ce5a6e8f7ff0ec8b8f7bbb732c6375 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 18:10:52 -0700
Subject: [PATCH 47/48] [Test] Keep trying the paths for ccache

---
 .github/workflows/build.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index bb280b890..c8ab2f484 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -149,7 +149,7 @@ jobs:
       - name: ccache cache files
         uses: actions/cache@v2
         with:
-          path: $ENV{GITHUB_WORKSPACE}/.ccache
+          path: ${{runner.workspace}}/.ccache
           key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }}
           restore-keys: |
             ${{ matrix.config.name }}-ccache-
@@ -158,7 +158,7 @@ jobs:
       - name: Configure ccache
         shell: cmake -P {0}
         run: |
-          file(TO_CMAKE_PATH "$ENV{GITHUB_WORKSPACE}" ccache_basedir)
+          file(TO_CMAKE_PATH ${{runner.workspace}} ccache_basedir)
           set(ENV{CCACHE_BASEDIR} "${ccache_basedir}")
           set(ENV{CCACHE_DIR} "${ccache_basedir}/.ccache")
           set(ENV{CCACHE_COMPRESS} "true")

From 96a99fcb6b70e61cc3cd3831f2ecc6bdda6372c9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Nov 2020 18:58:06 -0700
Subject: [PATCH 48/48] [Test] Change to short build name and see if ccache is
 working or not

---
 .github/workflows/build.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index c8ab2f484..2a698695e 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -1,4 +1,4 @@
-name: OpenFPGA Tests
+name: linux_build
 
 # Run CI on
 # - each push
@@ -19,7 +19,7 @@ env:
 # Multiple job to tests
 jobs:
   # Test the compilation compatibility
-  build:
+  linux_build:
     name: ${{ matrix.config.name }}
     runs-on: ${{ matrix.config.os }}