From d269472dafe64817ef4cdca21d4426612b5345e5 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 27 Sep 2019 14:00:57 -0600 Subject: [PATCH] Updated formality python script --- openfpga_flow/misc/formality_template.tcl | 20 ++++++ openfpga_flow/misc/modelsim_template.j2 | 8 --- .../{run_modelsim.py => run_formality.py} | 67 ++++++++++++------- 3 files changed, 63 insertions(+), 32 deletions(-) create mode 100644 openfpga_flow/misc/formality_template.tcl delete mode 100644 openfpga_flow/misc/modelsim_template.j2 rename openfpga_flow/scripts/{run_modelsim.py => run_formality.py} (50%) diff --git a/openfpga_flow/misc/formality_template.tcl b/openfpga_flow/misc/formality_template.tcl new file mode 100644 index 000000000..2eb607ae9 --- /dev/null +++ b/openfpga_flow/misc/formality_template.tcl @@ -0,0 +1,20 @@ +# = = = = = = = = = = = = = = = = = = = = = = +# Auto generated using OpenFPGA +# = = = = = = = = = = = = = = = = = = = = = = + +# Benchmark Source Files +read_verilog -container r -libname WORK -05 { ${SOURCE_DESIGN_FILES} } +set_top r:${SOURCE_TOP_MODULE} + +# Benchmark Implementation Files +read_verilog -container i -libname WORK -05 { ${IMPL_DESIGN_FILES} } +set_top i:${IMPL_TOP_DIR} + +match +# Port Mapping +${PORT_MAP_LIST} + +# Register Mapping +${REGISTER_MAP_LIST} + +verify diff --git a/openfpga_flow/misc/modelsim_template.j2 b/openfpga_flow/misc/modelsim_template.j2 deleted file mode 100644 index cfa43d11c..000000000 --- a/openfpga_flow/misc/modelsim_template.j2 +++ /dev/null @@ -1,8 +0,0 @@ -read_verilog -container r -libname WORK -05 { ${SOURCE_DESIGN} } -set_top r:${SOURCE_TOP_DIR} -read_verilog -container i -libname WORK -05 { ${IMPL_DESIGN} } - -set_top i:${IMPL_TOP_DIR} -match -${MATCH_MODUEL_LIST} -verify diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_formality.py similarity index 50% rename from openfpga_flow/scripts/run_modelsim.py rename to openfpga_flow/scripts/run_formality.py index e8dca5cb4..f1d781626 100644 --- a/openfpga_flow/scripts/run_modelsim.py +++ b/openfpga_flow/scripts/run_formality.py @@ -1,10 +1,12 @@ from string import Template import sys import os +import pprint import argparse import subprocess import logging from pprint import pprint +from configparser import ConfigParser # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configure logging system @@ -13,55 +15,72 @@ logging.basicConfig(level=logging.INFO, stream=sys.stdout, format='%(levelname)s (%(threadName)10s) - %(message)s') logger = logging.getLogger('Modelsim_run_log') +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Parse commandline arguments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = parser = argparse.ArgumentParser() parser.add_argument('files', nargs='+') -parser.add_argument('--modelsim_template', type=str, +parser.add_argument('--formality_template', type=str, help="Modelsim verification template file") parser.add_argument('--run_sim', action="store_true", help="Execute generated script in formality") args = parser.parse_args() - -if not args.modelsim_template: +# Consider default formality script template +if not args.formality_template: task_script_dir = os.path.dirname(os.path.abspath(__file__)) - args.modelsim_template = os.path.join(task_script_dir, os.pardir, - "misc", "modelsim_template.j2") + args.formality_template = os.path.join(task_script_dir, os.pardir, + "misc", "formality_template.tcl") -args.modelsim_template = os.path.abspath(args.modelsim_template) +args.formality_template = os.path.abspath(args.formality_template) def main(): for eachFile in args.files: eachFile = os.path.abspath(eachFile) - directory = os.path.dirname(eachFile) - os.chdir(directory) - with open(eachFile, 'r') as fp: - lines = fp.read().split("\n") - SplitL = [indx for indx, eachL in enumerate(lines) if eachL == ""] - SplitL = list(zip([0] + SplitL[:-1], SplitL)) - for indx, eachSection in enumerate(SplitL): - SplitL[indx] = list(filter(None, lines[slice(*eachSection)])) + pDir = os.path.dirname(eachFile) + os.chdir(pDir) - match_str = "set_user_match r:%s i:%s -type port -noninverted" - lables = {"SOURCE_DESIGN": " ".join(SplitL[0]), - "SOURCE_TOP_DIR": "/WORK/" + " ".join(SplitL[1]), - "IMPL_DESIGN": " ".join(SplitL[2]), - "IMPL_TOP_DIR": "/WORK/" + " ".join(SplitL[3]), - "MATCH_MODUEL_LIST": "\n".join([match_str % tuple(eachPort.split()) for eachPort in SplitL[4]]) - } + config = ConfigParser() + config.read(eachFile) - tmpl = Template(open(args.modelsim_template, encoding='utf-8').read()) - with open("Output.tcl", 'w', encoding='utf-8') as tclout: + port_map = ("set_user_match r:%s/%%s i:/WORK/%%s -type port -noninverted" % ( + "/WORK/" + config["BENCHMARK_INFO"]["src_top_module"] + )) + cell_map = ("set_user_match r:%s/%%s i:/WORK/%%s -type cell -noninverted" % ( + "/WORK/" + config["BENCHMARK_INFO"]["src_top_module"] + )) + + lables = { + "SOURCE_DESIGN_FILES": config["BENCHMARK_INFO"]["benchmark_netlist"], + "SOURCE_TOP_MODULE": "/WORK/" + config["BENCHMARK_INFO"]["src_top_module"], + + "IMPL_DESIGN_FILES": " ".join( + [val for key, val in config["FPGA_INFO"].items() + if "impl_netlist_" in key]), + "IMPL_TOP_DIR": "/WORK/" + config["FPGA_INFO"]["impl_top_module"], + + "PORT_MAP_LIST": "\n".join([port_map % + ele for ele in + config["PORT_MATCHING"].items()]), + "REGISTER_MAP_LIST": "\n".join([cell_map % + ele for ele in + config["REGISTER_MATCH"].items()]), + } + + tmpl = Template(open(args.formality_template, encoding='utf-8').read()) + with open(os.path.join(pDir, "Output.tcl"), 'w', encoding='utf-8') as tclout: tclout.write(tmpl.substitute(lables)) if args.run_sim: formality_run_string = ["formality", "-file", "Output.tcl"] - run_command("Modelsim run", "modelsim_run.log", formality_run_string) + run_command("Formality Run", "formality_run.log", formality_run_string) else: with open("Output.tcl", 'r', encoding='utf-8') as tclout: print(tclout.read()) def run_command(taskname, logfile, command, exit_if_fail=True): + os.chdir(os.pardir) logger.info("Launching %s " % taskname) with open(logfile, 'w+') as output: try: