diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index 5d9e929e2..6ed9c4edf 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.809066534 + #0.4880859554 clk[0] <= !clk[0]; end end @@ -106,7 +106,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #11.32693195 + #6.833203316 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 06fd83ed4..2ccec1ac6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -9,20 +9,19 @@ ################################################## # Create clock ################################################## -create_clock clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10} +create_clock clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} ################################################## # Create input and output delays for used I/Os ################################################## -set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[11] -set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[14] -set_output_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[12] +set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[11] +set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[14] +set_output_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[1] ################################################## # Disable timing for unused I/Os ################################################## set_disable_timing gfpga_pad_GPIO_PAD[0] -set_disable_timing gfpga_pad_GPIO_PAD[1] set_disable_timing gfpga_pad_GPIO_PAD[2] set_disable_timing gfpga_pad_GPIO_PAD[3] set_disable_timing gfpga_pad_GPIO_PAD[4] @@ -32,6 +31,7 @@ set_disable_timing gfpga_pad_GPIO_PAD[7] set_disable_timing gfpga_pad_GPIO_PAD[8] set_disable_timing gfpga_pad_GPIO_PAD[9] set_disable_timing gfpga_pad_GPIO_PAD[10] +set_disable_timing gfpga_pad_GPIO_PAD[12] set_disable_timing gfpga_pad_GPIO_PAD[13] set_disable_timing gfpga_pad_GPIO_PAD[15] set_disable_timing gfpga_pad_GPIO_PAD[16] @@ -156,9 +156,11 @@ set_disable_timing cbx_1__0_/chanx_left_in[7] set_disable_timing cbx_1__0_/chanx_right_in[7] set_disable_timing cbx_1__0_/chanx_left_in[8] set_disable_timing cbx_1__0_/chanx_right_in[8] +set_disable_timing cbx_1__0_/chanx_left_in[9] set_disable_timing cbx_1__0_/chanx_right_in[9] set_disable_timing cbx_1__0_/chanx_left_in[10] set_disable_timing cbx_1__0_/chanx_right_in[10] +set_disable_timing cbx_1__0_/chanx_left_in[11] set_disable_timing cbx_1__0_/chanx_right_in[11] set_disable_timing cbx_1__0_/chanx_left_in[12] set_disable_timing cbx_1__0_/chanx_right_in[12] @@ -180,9 +182,11 @@ set_disable_timing cbx_1__0_/chanx_left_out[7] set_disable_timing cbx_1__0_/chanx_right_out[7] set_disable_timing cbx_1__0_/chanx_left_out[8] set_disable_timing cbx_1__0_/chanx_right_out[8] +set_disable_timing cbx_1__0_/chanx_left_out[9] set_disable_timing cbx_1__0_/chanx_right_out[9] set_disable_timing cbx_1__0_/chanx_left_out[10] set_disable_timing cbx_1__0_/chanx_right_out[10] +set_disable_timing cbx_1__0_/chanx_left_out[11] set_disable_timing cbx_1__0_/chanx_right_out[11] set_disable_timing cbx_1__0_/chanx_left_out[12] set_disable_timing cbx_1__0_/chanx_right_out[12] @@ -272,6 +276,7 @@ set_disable_timing cbx_1__1_/chanx_left_in[1] set_disable_timing cbx_1__1_/chanx_left_in[2] set_disable_timing cbx_1__1_/chanx_right_in[2] set_disable_timing cbx_1__1_/chanx_left_in[3] +set_disable_timing cbx_1__1_/chanx_right_in[3] set_disable_timing cbx_1__1_/chanx_left_in[4] set_disable_timing cbx_1__1_/chanx_right_in[4] set_disable_timing cbx_1__1_/chanx_left_in[5] @@ -296,6 +301,7 @@ set_disable_timing cbx_1__1_/chanx_left_out[1] set_disable_timing cbx_1__1_/chanx_left_out[2] set_disable_timing cbx_1__1_/chanx_right_out[2] set_disable_timing cbx_1__1_/chanx_left_out[3] +set_disable_timing cbx_1__1_/chanx_right_out[3] set_disable_timing cbx_1__1_/chanx_left_out[4] set_disable_timing cbx_1__1_/chanx_right_out[4] set_disable_timing cbx_1__1_/chanx_left_out[5] @@ -315,7 +321,6 @@ set_disable_timing cbx_1__1_/chanx_right_out[11] set_disable_timing cbx_1__1_/chanx_left_out[12] set_disable_timing cbx_1__1_/chanx_right_out[12] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] -set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] @@ -334,7 +339,6 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[0] set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[3] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[1] set_disable_timing cbx_1__1_/mux_top_ipin_0/in[1] -set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[2] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[0] set_disable_timing cbx_1__1_/mux_top_ipin_0/in[0] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[3] @@ -411,9 +415,11 @@ set_disable_timing cby_0__1_/chany_top_in[6] set_disable_timing cby_0__1_/chany_bottom_in[7] set_disable_timing cby_0__1_/chany_top_in[7] set_disable_timing cby_0__1_/chany_bottom_in[8] +set_disable_timing cby_0__1_/chany_top_in[8] set_disable_timing cby_0__1_/chany_bottom_in[9] set_disable_timing cby_0__1_/chany_top_in[9] set_disable_timing cby_0__1_/chany_bottom_in[10] +set_disable_timing cby_0__1_/chany_top_in[10] set_disable_timing cby_0__1_/chany_bottom_in[11] set_disable_timing cby_0__1_/chany_top_in[11] set_disable_timing cby_0__1_/chany_bottom_in[12] @@ -435,9 +441,11 @@ set_disable_timing cby_0__1_/chany_top_out[6] set_disable_timing cby_0__1_/chany_bottom_out[7] set_disable_timing cby_0__1_/chany_top_out[7] set_disable_timing cby_0__1_/chany_bottom_out[8] +set_disable_timing cby_0__1_/chany_top_out[8] set_disable_timing cby_0__1_/chany_bottom_out[9] set_disable_timing cby_0__1_/chany_top_out[9] set_disable_timing cby_0__1_/chany_bottom_out[10] +set_disable_timing cby_0__1_/chany_top_out[10] set_disable_timing cby_0__1_/chany_bottom_out[11] set_disable_timing cby_0__1_/chany_top_out[11] set_disable_timing cby_0__1_/chany_bottom_out[12] @@ -518,9 +526,11 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4] set_disable_timing cby_1__1_/chany_top_in[0] set_disable_timing cby_1__1_/chany_bottom_in[1] set_disable_timing cby_1__1_/chany_top_in[1] +set_disable_timing cby_1__1_/chany_bottom_in[2] set_disable_timing cby_1__1_/chany_top_in[2] set_disable_timing cby_1__1_/chany_bottom_in[3] set_disable_timing cby_1__1_/chany_top_in[3] +set_disable_timing cby_1__1_/chany_bottom_in[4] set_disable_timing cby_1__1_/chany_top_in[4] set_disable_timing cby_1__1_/chany_bottom_in[5] set_disable_timing cby_1__1_/chany_top_in[5] @@ -539,9 +549,11 @@ set_disable_timing cby_1__1_/chany_top_in[12] set_disable_timing cby_1__1_/chany_top_out[0] set_disable_timing cby_1__1_/chany_bottom_out[1] set_disable_timing cby_1__1_/chany_top_out[1] +set_disable_timing cby_1__1_/chany_bottom_out[2] set_disable_timing cby_1__1_/chany_top_out[2] set_disable_timing cby_1__1_/chany_bottom_out[3] set_disable_timing cby_1__1_/chany_top_out[3] +set_disable_timing cby_1__1_/chany_bottom_out[4] set_disable_timing cby_1__1_/chany_top_out[4] set_disable_timing cby_1__1_/chany_bottom_out[5] set_disable_timing cby_1__1_/chany_top_out[5] @@ -561,6 +573,7 @@ set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_out set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] @@ -589,6 +602,7 @@ set_disable_timing cby_1__1_/mux_right_ipin_2/in[1] set_disable_timing cby_1__1_/mux_left_ipin_3/in[2] set_disable_timing cby_1__1_/mux_left_ipin_4/in[0] set_disable_timing cby_1__1_/mux_right_ipin_2/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[3] set_disable_timing cby_1__1_/mux_left_ipin_5/in[1] set_disable_timing cby_1__1_/mux_left_ipin_4/in[2] set_disable_timing cby_1__1_/mux_left_ipin_5/in[0] @@ -648,9 +662,11 @@ set_disable_timing sb_0__0_/chany_top_in[6] set_disable_timing sb_0__0_/chany_top_out[7] set_disable_timing sb_0__0_/chany_top_in[7] set_disable_timing sb_0__0_/chany_top_out[8] +set_disable_timing sb_0__0_/chany_top_in[8] set_disable_timing sb_0__0_/chany_top_out[9] set_disable_timing sb_0__0_/chany_top_in[9] set_disable_timing sb_0__0_/chany_top_out[10] +set_disable_timing sb_0__0_/chany_top_in[10] set_disable_timing sb_0__0_/chany_top_out[11] set_disable_timing sb_0__0_/chany_top_in[11] set_disable_timing sb_0__0_/chany_top_out[12] @@ -673,9 +689,11 @@ set_disable_timing sb_0__0_/chanx_right_out[7] set_disable_timing sb_0__0_/chanx_right_in[7] set_disable_timing sb_0__0_/chanx_right_out[8] set_disable_timing sb_0__0_/chanx_right_in[8] +set_disable_timing sb_0__0_/chanx_right_out[9] set_disable_timing sb_0__0_/chanx_right_in[9] set_disable_timing sb_0__0_/chanx_right_out[10] set_disable_timing sb_0__0_/chanx_right_in[10] +set_disable_timing sb_0__0_/chanx_right_out[11] set_disable_timing sb_0__0_/chanx_right_in[11] set_disable_timing sb_0__0_/chanx_right_out[12] set_disable_timing sb_0__0_/chanx_right_in[12] @@ -757,7 +775,9 @@ set_disable_timing sb_0__0_/mux_right_track_10/in[0] set_disable_timing sb_0__0_/mux_right_track_12/in[0] set_disable_timing sb_0__0_/mux_right_track_14/in[0] set_disable_timing sb_0__0_/mux_right_track_16/in[0] +set_disable_timing sb_0__0_/mux_right_track_18/in[0] set_disable_timing sb_0__0_/mux_right_track_20/in[0] +set_disable_timing sb_0__0_/mux_right_track_22/in[0] set_disable_timing sb_0__0_/mux_right_track_24/in[0] set_disable_timing sb_0__0_/mux_right_track_0/in[0] set_disable_timing sb_0__0_/mux_top_track_24/in[2] @@ -782,6 +802,7 @@ set_disable_timing sb_0__1_/chanx_right_out[1] set_disable_timing sb_0__1_/chanx_right_out[2] set_disable_timing sb_0__1_/chanx_right_in[2] set_disable_timing sb_0__1_/chanx_right_out[3] +set_disable_timing sb_0__1_/chanx_right_in[3] set_disable_timing sb_0__1_/chanx_right_out[4] set_disable_timing sb_0__1_/chanx_right_in[4] set_disable_timing sb_0__1_/chanx_right_out[5] @@ -817,9 +838,11 @@ set_disable_timing sb_0__1_/chany_bottom_out[6] set_disable_timing sb_0__1_/chany_bottom_in[7] set_disable_timing sb_0__1_/chany_bottom_out[7] set_disable_timing sb_0__1_/chany_bottom_in[8] +set_disable_timing sb_0__1_/chany_bottom_out[8] set_disable_timing sb_0__1_/chany_bottom_in[9] set_disable_timing sb_0__1_/chany_bottom_out[9] set_disable_timing sb_0__1_/chany_bottom_in[10] +set_disable_timing sb_0__1_/chany_bottom_out[10] set_disable_timing sb_0__1_/chany_bottom_in[11] set_disable_timing sb_0__1_/chany_bottom_out[11] set_disable_timing sb_0__1_/chany_bottom_in[12] @@ -893,7 +916,9 @@ set_disable_timing sb_0__1_/mux_bottom_track_3/in[3] set_disable_timing sb_0__1_/mux_bottom_track_15/in[3] set_disable_timing sb_0__1_/mux_bottom_track_17/in[2] set_disable_timing sb_0__1_/mux_bottom_track_23/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_21/in[0] set_disable_timing sb_0__1_/mux_bottom_track_19/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_17/in[0] set_disable_timing sb_0__1_/mux_bottom_track_15/in[0] set_disable_timing sb_0__1_/mux_bottom_track_13/in[0] set_disable_timing sb_0__1_/mux_bottom_track_11/in[0] @@ -922,9 +947,11 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2] set_disable_timing sb_1__0_/chany_top_in[0] set_disable_timing sb_1__0_/chany_top_out[1] set_disable_timing sb_1__0_/chany_top_in[1] +set_disable_timing sb_1__0_/chany_top_out[2] set_disable_timing sb_1__0_/chany_top_in[2] set_disable_timing sb_1__0_/chany_top_out[3] set_disable_timing sb_1__0_/chany_top_in[3] +set_disable_timing sb_1__0_/chany_top_out[4] set_disable_timing sb_1__0_/chany_top_in[4] set_disable_timing sb_1__0_/chany_top_out[5] set_disable_timing sb_1__0_/chany_top_in[5] @@ -958,9 +985,11 @@ set_disable_timing sb_1__0_/chanx_left_in[7] set_disable_timing sb_1__0_/chanx_left_out[7] set_disable_timing sb_1__0_/chanx_left_in[8] set_disable_timing sb_1__0_/chanx_left_out[8] +set_disable_timing sb_1__0_/chanx_left_in[9] set_disable_timing sb_1__0_/chanx_left_out[9] set_disable_timing sb_1__0_/chanx_left_in[10] set_disable_timing sb_1__0_/chanx_left_out[10] +set_disable_timing sb_1__0_/chanx_left_in[11] set_disable_timing sb_1__0_/chanx_left_out[11] set_disable_timing sb_1__0_/chanx_left_in[12] set_disable_timing sb_1__0_/chanx_left_out[12] @@ -1050,7 +1079,9 @@ set_disable_timing sb_1__0_/mux_top_track_16/in[2] set_disable_timing sb_1__0_/mux_top_track_14/in[3] set_disable_timing sb_1__0_/mux_top_track_12/in[2] set_disable_timing sb_1__0_/mux_top_track_10/in[2] +set_disable_timing sb_1__0_/mux_top_track_8/in[2] set_disable_timing sb_1__0_/mux_top_track_6/in[2] +set_disable_timing sb_1__0_/mux_top_track_4/in[2] set_disable_timing sb_1__0_/mux_top_track_2/in[3] ################################################## # Disable timing for Switch block sb_1__1_ @@ -1058,9 +1089,11 @@ set_disable_timing sb_1__0_/mux_top_track_2/in[3] set_disable_timing sb_1__1_/chany_bottom_out[0] set_disable_timing sb_1__1_/chany_bottom_in[1] set_disable_timing sb_1__1_/chany_bottom_out[1] +set_disable_timing sb_1__1_/chany_bottom_in[2] set_disable_timing sb_1__1_/chany_bottom_out[2] set_disable_timing sb_1__1_/chany_bottom_in[3] set_disable_timing sb_1__1_/chany_bottom_out[3] +set_disable_timing sb_1__1_/chany_bottom_in[4] set_disable_timing sb_1__1_/chany_bottom_out[4] set_disable_timing sb_1__1_/chany_bottom_in[5] set_disable_timing sb_1__1_/chany_bottom_out[5] @@ -1082,6 +1115,7 @@ set_disable_timing sb_1__1_/chanx_left_in[1] set_disable_timing sb_1__1_/chanx_left_in[2] set_disable_timing sb_1__1_/chanx_left_out[2] set_disable_timing sb_1__1_/chanx_left_in[3] +set_disable_timing sb_1__1_/chanx_left_out[3] set_disable_timing sb_1__1_/chanx_left_in[4] set_disable_timing sb_1__1_/chanx_left_out[4] set_disable_timing sb_1__1_/chanx_left_in[5] @@ -1166,6 +1200,7 @@ set_disable_timing sb_1__1_/mux_left_track_13/in[3] set_disable_timing sb_1__1_/mux_left_track_15/in[2] set_disable_timing sb_1__1_/mux_left_track_17/in[2] set_disable_timing sb_1__1_/mux_left_track_5/in[0] +set_disable_timing sb_1__1_/mux_left_track_7/in[0] set_disable_timing sb_1__1_/mux_left_track_9/in[0] set_disable_timing sb_1__1_/mux_left_track_11/in[0] set_disable_timing sb_1__1_/mux_left_track_13/in[0] @@ -1431,16 +1466,20 @@ set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/* ####################################### set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused grid[1][2][1] +# Disable Timing for unused resources in grid[1][2][1] ####################################### ####################################### -# Disable all the ports for pb_graph_node io[0] +# Disable unused pins for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/* +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/io_inpad[0] ####################################### -# Disable all the ports for pb_graph_node iopad[0] +# Disable unused mux_inputs for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] ####################################### # Disable Timing for unused grid[1][2][2] ####################################### @@ -1559,20 +1598,16 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc ####################################### set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] ####################################### -# Disable Timing for unused resources in grid[2][1][4] +# Disable Timing for unused grid[2][1][4] ####################################### ####################################### -# Disable unused pins for pb_graph_node io[0] +# Disable all the ports for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0] +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/* ####################################### -# Disable unused mux_inputs for pb_graph_node io[0] +# Disable all the ports for pb_graph_node iopad[0] ####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0] -####################################### -# Disable unused pins for pb_graph_node iopad[0] -####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* ####################################### # Disable Timing for unused grid[2][1][5] ####################################### diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v index 5608bef83..53f34c9c4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -45,12 +45,11 @@ wire [0:0] clk_fm; // ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[14] ----- assign gfpga_pad_GPIO_PAD_fm[14] = b[0]; -// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] ----- - assign c[0] = gfpga_pad_GPIO_PAD_fm[12]; +// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[1] ----- + assign c[0] = gfpga_pad_GPIO_PAD_fm[1]; // ----- Wire unused FPGA I/Os to constants ----- assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0; - assign gfpga_pad_GPIO_PAD_fm[1] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0; @@ -60,6 +59,7 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0; @@ -132,8 +132,8 @@ initial begin force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; @@ -154,8 +154,8 @@ initial begin force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; - force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; @@ -238,12 +238,12 @@ initial begin force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; @@ -288,12 +288,12 @@ initial begin force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; @@ -302,12 +302,12 @@ initial begin force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10; - force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10; - force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; @@ -382,8 +382,8 @@ initial begin force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; @@ -426,8 +426,8 @@ initial begin force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = 3'b001; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = 3'b110; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}}; @@ -474,8 +474,8 @@ initial begin force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101; - force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}}; diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit index f116aa10c..7c8512c57 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -155,31 +155,6 @@ 0 0 0 -1 -0 -1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 0 0 0 @@ -223,7 +198,32 @@ 0 0 1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 1 @@ -301,12 +301,12 @@ 0 0 0 -1 -1 0 0 -1 -1 +0 +0 +0 +0 0 0 0 @@ -360,11 +360,6 @@ 1 1 1 -1 -1 -1 -1 -1 0 1 1 @@ -378,6 +373,11 @@ 1 1 1 +1 +1 +1 +1 +1 0 0 0 @@ -459,11 +459,11 @@ 0 0 0 -1 0 0 0 -1 +0 +0 0 0 0 @@ -472,12 +472,12 @@ 1 0 0 -1 -1 -0 -0 -1 -1 +0 +0 +0 +0 +0 +0 0 0 0 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml index 12a7a85bd..c42176d6b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -314,11 +314,11 @@ - + - + @@ -398,7 +398,7 @@ - + @@ -448,9 +448,9 @@ - + - + @@ -606,17 +606,17 @@ - + - + - + - + @@ -724,7 +724,7 @@ - + @@ -734,7 +734,7 @@ - + @@ -922,7 +922,7 @@ - + @@ -930,7 +930,7 @@ - + @@ -948,17 +948,17 @@ - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml index 283d346ab..1b1ecfa0d 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml @@ -553,7 +553,7 @@ - + @@ -731,7 +731,7 @@ - + @@ -1480,15 +1480,15 @@ - + - + - - - + + + @@ -1516,15 +1516,15 @@ - + - + - - - + + + @@ -1961,16 +1961,16 @@ - + - + - - - + + + @@ -2002,11 +2002,11 @@ - + - - - + + + @@ -2098,13 +2098,13 @@ - + - + - - + + @@ -2136,13 +2136,13 @@ - + - + - - + + @@ -2864,16 +2864,16 @@ - + - + - - - + + + @@ -2902,7 +2902,7 @@ - + @@ -3128,7 +3128,7 @@ - + @@ -3174,7 +3174,7 @@ - + @@ -3266,7 +3266,7 @@ - + @@ -3287,7 +3287,7 @@ - + @@ -3341,12 +3341,12 @@ - + - + - + @@ -3382,7 +3382,7 @@ - + @@ -3403,7 +3403,7 @@ - + @@ -3541,7 +3541,7 @@ - + @@ -3616,7 +3616,7 @@ - + @@ -3662,7 +3662,7 @@ - + @@ -3754,7 +3754,7 @@ - + @@ -3775,7 +3775,7 @@ - + @@ -3845,7 +3845,7 @@ - + @@ -3866,7 +3866,7 @@ - + @@ -3891,18 +3891,18 @@ - + - + - - + + - + @@ -3912,7 +3912,7 @@ - + @@ -4004,7 +4004,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc index c169fa409..f072bac09 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc @@ -14,7 +14,7 @@ set_units -time s ################################################## # Create clock ################################################## -create_clock -name clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10} [get_ports {clk[0]}] +create_clock -name clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} [get_ports {clk[0]}] ################################################## # Create programmable clock ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml index 9e63dda8a..89523007a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml @@ -5,5 +5,5 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index b7419a519..5a6b6b31a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.782782793 + #0.8625563979 clk[0] <= !clk[0]; end end @@ -106,7 +106,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #10.95895958 + #12.07578945 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 99d159133..3ef8489eb 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -9,14 +9,14 @@ ################################################## # Create clock ################################################## -create_clock clk[0] -period 1.565565566e-09 -waveform {0 7.82782783e-10} +create_clock clk[0] -period 1.725112719e-09 -waveform {0 8.625563597e-10} ################################################## # Create input and output delays for used I/Os ################################################## -set_input_delay -clock clk[0] -max 1.565565566e-09 gfpga_pad_GPIO_PAD[79] -set_input_delay -clock clk[0] -max 1.565565566e-09 gfpga_pad_GPIO_PAD[74] -set_output_delay -clock clk[0] -max 1.565565566e-09 gfpga_pad_GPIO_PAD[17] +set_input_delay -clock clk[0] -max 1.725112719e-09 gfpga_pad_GPIO_PAD[38] +set_input_delay -clock clk[0] -max 1.725112719e-09 gfpga_pad_GPIO_PAD[58] +set_output_delay -clock clk[0] -max 1.725112719e-09 gfpga_pad_GPIO_PAD[17] ################################################## # Disable timing for unused I/Os @@ -58,7 +58,6 @@ set_disable_timing gfpga_pad_GPIO_PAD[34] set_disable_timing gfpga_pad_GPIO_PAD[35] set_disable_timing gfpga_pad_GPIO_PAD[36] set_disable_timing gfpga_pad_GPIO_PAD[37] -set_disable_timing gfpga_pad_GPIO_PAD[38] set_disable_timing gfpga_pad_GPIO_PAD[39] set_disable_timing gfpga_pad_GPIO_PAD[40] set_disable_timing gfpga_pad_GPIO_PAD[41] @@ -78,7 +77,6 @@ set_disable_timing gfpga_pad_GPIO_PAD[54] set_disable_timing gfpga_pad_GPIO_PAD[55] set_disable_timing gfpga_pad_GPIO_PAD[56] set_disable_timing gfpga_pad_GPIO_PAD[57] -set_disable_timing gfpga_pad_GPIO_PAD[58] set_disable_timing gfpga_pad_GPIO_PAD[59] set_disable_timing gfpga_pad_GPIO_PAD[60] set_disable_timing gfpga_pad_GPIO_PAD[61] @@ -94,10 +92,12 @@ set_disable_timing gfpga_pad_GPIO_PAD[70] set_disable_timing gfpga_pad_GPIO_PAD[71] set_disable_timing gfpga_pad_GPIO_PAD[72] set_disable_timing gfpga_pad_GPIO_PAD[73] +set_disable_timing gfpga_pad_GPIO_PAD[74] set_disable_timing gfpga_pad_GPIO_PAD[75] set_disable_timing gfpga_pad_GPIO_PAD[76] set_disable_timing gfpga_pad_GPIO_PAD[77] set_disable_timing gfpga_pad_GPIO_PAD[78] +set_disable_timing gfpga_pad_GPIO_PAD[79] set_disable_timing gfpga_pad_GPIO_PAD[80] set_disable_timing gfpga_pad_GPIO_PAD[81] set_disable_timing gfpga_pad_GPIO_PAD[82] @@ -468,7 +468,6 @@ set_disable_timing cbx_1__2_/chanx_right_in[0] set_disable_timing cbx_1__2_/chanx_left_in[1] set_disable_timing cbx_1__2_/chanx_right_in[1] set_disable_timing cbx_1__2_/chanx_left_in[2] -set_disable_timing cbx_1__2_/chanx_right_in[2] set_disable_timing cbx_1__2_/chanx_left_in[3] set_disable_timing cbx_1__2_/chanx_right_in[3] set_disable_timing cbx_1__2_/chanx_left_in[4] @@ -478,7 +477,6 @@ set_disable_timing cbx_1__2_/chanx_right_in[5] set_disable_timing cbx_1__2_/chanx_left_in[6] set_disable_timing cbx_1__2_/chanx_right_in[6] set_disable_timing cbx_1__2_/chanx_left_in[7] -set_disable_timing cbx_1__2_/chanx_right_in[7] set_disable_timing cbx_1__2_/chanx_left_in[8] set_disable_timing cbx_1__2_/chanx_right_in[8] set_disable_timing cbx_1__2_/chanx_left_in[9] @@ -488,7 +486,6 @@ set_disable_timing cbx_1__2_/chanx_right_out[0] set_disable_timing cbx_1__2_/chanx_left_out[1] set_disable_timing cbx_1__2_/chanx_right_out[1] set_disable_timing cbx_1__2_/chanx_left_out[2] -set_disable_timing cbx_1__2_/chanx_right_out[2] set_disable_timing cbx_1__2_/chanx_left_out[3] set_disable_timing cbx_1__2_/chanx_right_out[3] set_disable_timing cbx_1__2_/chanx_left_out[4] @@ -498,7 +495,6 @@ set_disable_timing cbx_1__2_/chanx_right_out[5] set_disable_timing cbx_1__2_/chanx_left_out[6] set_disable_timing cbx_1__2_/chanx_right_out[6] set_disable_timing cbx_1__2_/chanx_left_out[7] -set_disable_timing cbx_1__2_/chanx_right_out[7] set_disable_timing cbx_1__2_/chanx_left_out[8] set_disable_timing cbx_1__2_/chanx_right_out[8] set_disable_timing cbx_1__2_/chanx_left_out[9] @@ -716,6 +712,7 @@ set_disable_timing cbx_2__0_/chanx_right_in[7] set_disable_timing cbx_2__0_/chanx_left_in[8] set_disable_timing cbx_2__0_/chanx_right_in[8] set_disable_timing cbx_2__0_/chanx_left_in[9] +set_disable_timing cbx_2__0_/chanx_right_in[9] set_disable_timing cbx_2__0_/chanx_left_out[0] set_disable_timing cbx_2__0_/chanx_right_out[0] set_disable_timing cbx_2__0_/chanx_left_out[1] @@ -735,6 +732,7 @@ set_disable_timing cbx_2__0_/chanx_right_out[7] set_disable_timing cbx_2__0_/chanx_left_out[8] set_disable_timing cbx_2__0_/chanx_right_out[8] set_disable_timing cbx_2__0_/chanx_left_out[9] +set_disable_timing cbx_2__0_/chanx_right_out[9] set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] set_disable_timing cbx_2__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] @@ -798,7 +796,6 @@ set_disable_timing cbx_2__1_/chanx_right_in[1] set_disable_timing cbx_2__1_/chanx_left_in[2] set_disable_timing cbx_2__1_/chanx_right_in[2] set_disable_timing cbx_2__1_/chanx_left_in[3] -set_disable_timing cbx_2__1_/chanx_right_in[3] set_disable_timing cbx_2__1_/chanx_left_in[4] set_disable_timing cbx_2__1_/chanx_right_in[4] set_disable_timing cbx_2__1_/chanx_left_in[5] @@ -818,7 +815,6 @@ set_disable_timing cbx_2__1_/chanx_right_out[1] set_disable_timing cbx_2__1_/chanx_left_out[2] set_disable_timing cbx_2__1_/chanx_right_out[2] set_disable_timing cbx_2__1_/chanx_left_out[3] -set_disable_timing cbx_2__1_/chanx_right_out[3] set_disable_timing cbx_2__1_/chanx_left_out[4] set_disable_timing cbx_2__1_/chanx_right_out[4] set_disable_timing cbx_2__1_/chanx_left_out[5] @@ -863,7 +859,6 @@ set_disable_timing cbx_2__1_/mux_top_ipin_1/in[2] set_disable_timing cbx_2__2_/chanx_left_in[0] set_disable_timing cbx_2__2_/chanx_right_in[0] set_disable_timing cbx_2__2_/chanx_left_in[1] -set_disable_timing cbx_2__2_/chanx_right_in[1] set_disable_timing cbx_2__2_/chanx_left_in[2] set_disable_timing cbx_2__2_/chanx_right_in[2] set_disable_timing cbx_2__2_/chanx_left_in[3] @@ -873,16 +868,15 @@ set_disable_timing cbx_2__2_/chanx_right_in[4] set_disable_timing cbx_2__2_/chanx_left_in[5] set_disable_timing cbx_2__2_/chanx_right_in[5] set_disable_timing cbx_2__2_/chanx_left_in[6] -set_disable_timing cbx_2__2_/chanx_right_in[6] set_disable_timing cbx_2__2_/chanx_left_in[7] set_disable_timing cbx_2__2_/chanx_right_in[7] set_disable_timing cbx_2__2_/chanx_left_in[8] set_disable_timing cbx_2__2_/chanx_right_in[8] set_disable_timing cbx_2__2_/chanx_left_in[9] +set_disable_timing cbx_2__2_/chanx_right_in[9] set_disable_timing cbx_2__2_/chanx_left_out[0] set_disable_timing cbx_2__2_/chanx_right_out[0] set_disable_timing cbx_2__2_/chanx_left_out[1] -set_disable_timing cbx_2__2_/chanx_right_out[1] set_disable_timing cbx_2__2_/chanx_left_out[2] set_disable_timing cbx_2__2_/chanx_right_out[2] set_disable_timing cbx_2__2_/chanx_left_out[3] @@ -892,12 +886,12 @@ set_disable_timing cbx_2__2_/chanx_right_out[4] set_disable_timing cbx_2__2_/chanx_left_out[5] set_disable_timing cbx_2__2_/chanx_right_out[5] set_disable_timing cbx_2__2_/chanx_left_out[6] -set_disable_timing cbx_2__2_/chanx_right_out[6] set_disable_timing cbx_2__2_/chanx_left_out[7] set_disable_timing cbx_2__2_/chanx_right_out[7] set_disable_timing cbx_2__2_/chanx_left_out[8] set_disable_timing cbx_2__2_/chanx_right_out[8] set_disable_timing cbx_2__2_/chanx_left_out[9] +set_disable_timing cbx_2__2_/chanx_right_out[9] set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] set_disable_timing cbx_2__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] @@ -942,10 +936,10 @@ set_disable_timing cbx_2__3_/chanx_right_in[5] set_disable_timing cbx_2__3_/chanx_left_in[6] set_disable_timing cbx_2__3_/chanx_right_in[6] set_disable_timing cbx_2__3_/chanx_left_in[7] -set_disable_timing cbx_2__3_/chanx_right_in[7] set_disable_timing cbx_2__3_/chanx_left_in[8] set_disable_timing cbx_2__3_/chanx_right_in[8] set_disable_timing cbx_2__3_/chanx_left_in[9] +set_disable_timing cbx_2__3_/chanx_right_in[9] set_disable_timing cbx_2__3_/chanx_left_out[0] set_disable_timing cbx_2__3_/chanx_right_out[0] set_disable_timing cbx_2__3_/chanx_left_out[1] @@ -961,10 +955,10 @@ set_disable_timing cbx_2__3_/chanx_right_out[5] set_disable_timing cbx_2__3_/chanx_left_out[6] set_disable_timing cbx_2__3_/chanx_right_out[6] set_disable_timing cbx_2__3_/chanx_left_out[7] -set_disable_timing cbx_2__3_/chanx_right_out[7] set_disable_timing cbx_2__3_/chanx_left_out[8] set_disable_timing cbx_2__3_/chanx_right_out[8] set_disable_timing cbx_2__3_/chanx_left_out[9] +set_disable_timing cbx_2__3_/chanx_right_out[9] set_disable_timing cbx_2__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] set_disable_timing cbx_2__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] set_disable_timing cbx_2__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] @@ -1088,6 +1082,7 @@ set_disable_timing cbx_2__4_/mux_top_ipin_1/in[2] ################################################## # Disable timing for Connection block cbx_1__0_ ################################################## +set_disable_timing cbx_3__0_/chanx_left_in[0] set_disable_timing cbx_3__0_/chanx_right_in[0] set_disable_timing cbx_3__0_/chanx_left_in[1] set_disable_timing cbx_3__0_/chanx_right_in[1] @@ -1104,8 +1099,10 @@ set_disable_timing cbx_3__0_/chanx_right_in[6] set_disable_timing cbx_3__0_/chanx_left_in[7] set_disable_timing cbx_3__0_/chanx_right_in[7] set_disable_timing cbx_3__0_/chanx_left_in[8] +set_disable_timing cbx_3__0_/chanx_right_in[8] set_disable_timing cbx_3__0_/chanx_left_in[9] set_disable_timing cbx_3__0_/chanx_right_in[9] +set_disable_timing cbx_3__0_/chanx_left_out[0] set_disable_timing cbx_3__0_/chanx_right_out[0] set_disable_timing cbx_3__0_/chanx_left_out[1] set_disable_timing cbx_3__0_/chanx_right_out[1] @@ -1122,6 +1119,7 @@ set_disable_timing cbx_3__0_/chanx_right_out[6] set_disable_timing cbx_3__0_/chanx_left_out[7] set_disable_timing cbx_3__0_/chanx_right_out[7] set_disable_timing cbx_3__0_/chanx_left_out[8] +set_disable_timing cbx_3__0_/chanx_right_out[8] set_disable_timing cbx_3__0_/chanx_left_out[9] set_disable_timing cbx_3__0_/chanx_right_out[9] set_disable_timing cbx_3__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] @@ -1180,11 +1178,11 @@ set_disable_timing cbx_3__0_/mux_top_ipin_6/in[2] ################################################## # Disable timing for Connection block cbx_1__1_ ################################################## +set_disable_timing cbx_3__1_/chanx_left_in[0] set_disable_timing cbx_3__1_/chanx_right_in[0] set_disable_timing cbx_3__1_/chanx_left_in[1] set_disable_timing cbx_3__1_/chanx_right_in[1] set_disable_timing cbx_3__1_/chanx_left_in[2] -set_disable_timing cbx_3__1_/chanx_right_in[2] set_disable_timing cbx_3__1_/chanx_left_in[3] set_disable_timing cbx_3__1_/chanx_right_in[3] set_disable_timing cbx_3__1_/chanx_left_in[4] @@ -1199,11 +1197,11 @@ set_disable_timing cbx_3__1_/chanx_left_in[8] set_disable_timing cbx_3__1_/chanx_right_in[8] set_disable_timing cbx_3__1_/chanx_left_in[9] set_disable_timing cbx_3__1_/chanx_right_in[9] +set_disable_timing cbx_3__1_/chanx_left_out[0] set_disable_timing cbx_3__1_/chanx_right_out[0] set_disable_timing cbx_3__1_/chanx_left_out[1] set_disable_timing cbx_3__1_/chanx_right_out[1] set_disable_timing cbx_3__1_/chanx_left_out[2] -set_disable_timing cbx_3__1_/chanx_right_out[2] set_disable_timing cbx_3__1_/chanx_left_out[3] set_disable_timing cbx_3__1_/chanx_right_out[3] set_disable_timing cbx_3__1_/chanx_left_out[4] @@ -1218,11 +1216,13 @@ set_disable_timing cbx_3__1_/chanx_left_out[8] set_disable_timing cbx_3__1_/chanx_right_out[8] set_disable_timing cbx_3__1_/chanx_left_out[9] set_disable_timing cbx_3__1_/chanx_right_out[9] +set_disable_timing cbx_3__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] set_disable_timing cbx_3__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] set_disable_timing cbx_3__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] set_disable_timing cbx_3__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] set_disable_timing cbx_3__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] set_disable_timing cbx_3__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] +set_disable_timing cbx_3__1_/mux_bottom_ipin_0/in[1] set_disable_timing cbx_3__1_/mux_bottom_ipin_0/in[0] set_disable_timing cbx_3__1_/mux_bottom_ipin_1/in[1] set_disable_timing cbx_3__1_/mux_bottom_ipin_1/in[0] @@ -1246,7 +1246,6 @@ set_disable_timing cbx_3__1_/mux_top_ipin_1/in[2] # Disable timing for Connection block cbx_1__1_ ################################################## set_disable_timing cbx_3__2_/chanx_left_in[0] -set_disable_timing cbx_3__2_/chanx_right_in[0] set_disable_timing cbx_3__2_/chanx_left_in[1] set_disable_timing cbx_3__2_/chanx_right_in[1] set_disable_timing cbx_3__2_/chanx_left_in[2] @@ -1256,16 +1255,15 @@ set_disable_timing cbx_3__2_/chanx_right_in[3] set_disable_timing cbx_3__2_/chanx_left_in[4] set_disable_timing cbx_3__2_/chanx_right_in[4] set_disable_timing cbx_3__2_/chanx_left_in[5] -set_disable_timing cbx_3__2_/chanx_right_in[5] set_disable_timing cbx_3__2_/chanx_left_in[6] set_disable_timing cbx_3__2_/chanx_right_in[6] set_disable_timing cbx_3__2_/chanx_left_in[7] set_disable_timing cbx_3__2_/chanx_right_in[7] set_disable_timing cbx_3__2_/chanx_left_in[8] +set_disable_timing cbx_3__2_/chanx_right_in[8] set_disable_timing cbx_3__2_/chanx_left_in[9] set_disable_timing cbx_3__2_/chanx_right_in[9] set_disable_timing cbx_3__2_/chanx_left_out[0] -set_disable_timing cbx_3__2_/chanx_right_out[0] set_disable_timing cbx_3__2_/chanx_left_out[1] set_disable_timing cbx_3__2_/chanx_right_out[1] set_disable_timing cbx_3__2_/chanx_left_out[2] @@ -1275,17 +1273,18 @@ set_disable_timing cbx_3__2_/chanx_right_out[3] set_disable_timing cbx_3__2_/chanx_left_out[4] set_disable_timing cbx_3__2_/chanx_right_out[4] set_disable_timing cbx_3__2_/chanx_left_out[5] -set_disable_timing cbx_3__2_/chanx_right_out[5] set_disable_timing cbx_3__2_/chanx_left_out[6] set_disable_timing cbx_3__2_/chanx_right_out[6] set_disable_timing cbx_3__2_/chanx_left_out[7] set_disable_timing cbx_3__2_/chanx_right_out[7] set_disable_timing cbx_3__2_/chanx_left_out[8] +set_disable_timing cbx_3__2_/chanx_right_out[8] set_disable_timing cbx_3__2_/chanx_left_out[9] set_disable_timing cbx_3__2_/chanx_right_out[9] set_disable_timing cbx_3__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] set_disable_timing cbx_3__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] set_disable_timing cbx_3__2_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] +set_disable_timing cbx_3__2_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] set_disable_timing cbx_3__2_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] set_disable_timing cbx_3__2_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] set_disable_timing cbx_3__2_/mux_bottom_ipin_0/in[1] @@ -1305,6 +1304,7 @@ set_disable_timing cbx_3__2_/mux_top_ipin_2/in[0] set_disable_timing cbx_3__2_/mux_bottom_ipin_2/in[3] set_disable_timing cbx_3__2_/mux_bottom_ipin_2/in[2] set_disable_timing cbx_3__2_/mux_top_ipin_0/in[3] +set_disable_timing cbx_3__2_/mux_top_ipin_0/in[2] set_disable_timing cbx_3__2_/mux_top_ipin_1/in[3] set_disable_timing cbx_3__2_/mux_top_ipin_1/in[2] ################################################## @@ -1323,10 +1323,10 @@ set_disable_timing cbx_3__3_/chanx_right_in[4] set_disable_timing cbx_3__3_/chanx_left_in[5] set_disable_timing cbx_3__3_/chanx_right_in[5] set_disable_timing cbx_3__3_/chanx_left_in[6] -set_disable_timing cbx_3__3_/chanx_right_in[6] set_disable_timing cbx_3__3_/chanx_left_in[7] set_disable_timing cbx_3__3_/chanx_right_in[7] set_disable_timing cbx_3__3_/chanx_left_in[8] +set_disable_timing cbx_3__3_/chanx_right_in[8] set_disable_timing cbx_3__3_/chanx_left_in[9] set_disable_timing cbx_3__3_/chanx_right_in[9] set_disable_timing cbx_3__3_/chanx_left_out[0] @@ -1342,10 +1342,10 @@ set_disable_timing cbx_3__3_/chanx_right_out[4] set_disable_timing cbx_3__3_/chanx_left_out[5] set_disable_timing cbx_3__3_/chanx_right_out[5] set_disable_timing cbx_3__3_/chanx_left_out[6] -set_disable_timing cbx_3__3_/chanx_right_out[6] set_disable_timing cbx_3__3_/chanx_left_out[7] set_disable_timing cbx_3__3_/chanx_right_out[7] set_disable_timing cbx_3__3_/chanx_left_out[8] +set_disable_timing cbx_3__3_/chanx_right_out[8] set_disable_timing cbx_3__3_/chanx_left_out[9] set_disable_timing cbx_3__3_/chanx_right_out[9] set_disable_timing cbx_3__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] @@ -1471,6 +1471,7 @@ set_disable_timing cbx_3__4_/mux_top_ipin_1/in[2] ################################################## set_disable_timing cbx_4__0_/chanx_left_in[0] set_disable_timing cbx_4__0_/chanx_right_in[0] +set_disable_timing cbx_4__0_/chanx_left_in[1] set_disable_timing cbx_4__0_/chanx_right_in[1] set_disable_timing cbx_4__0_/chanx_left_in[2] set_disable_timing cbx_4__0_/chanx_right_in[2] @@ -1490,6 +1491,7 @@ set_disable_timing cbx_4__0_/chanx_left_in[9] set_disable_timing cbx_4__0_/chanx_right_in[9] set_disable_timing cbx_4__0_/chanx_left_out[0] set_disable_timing cbx_4__0_/chanx_right_out[0] +set_disable_timing cbx_4__0_/chanx_left_out[1] set_disable_timing cbx_4__0_/chanx_right_out[1] set_disable_timing cbx_4__0_/chanx_left_out[2] set_disable_timing cbx_4__0_/chanx_right_out[2] @@ -1565,7 +1567,7 @@ set_disable_timing cbx_4__0_/mux_top_ipin_6/in[2] ################################################## set_disable_timing cbx_4__1_/chanx_left_in[0] set_disable_timing cbx_4__1_/chanx_right_in[0] -set_disable_timing cbx_4__1_/chanx_right_in[1] +set_disable_timing cbx_4__1_/chanx_left_in[1] set_disable_timing cbx_4__1_/chanx_left_in[2] set_disable_timing cbx_4__1_/chanx_right_in[2] set_disable_timing cbx_4__1_/chanx_left_in[3] @@ -1584,7 +1586,7 @@ set_disable_timing cbx_4__1_/chanx_left_in[9] set_disable_timing cbx_4__1_/chanx_right_in[9] set_disable_timing cbx_4__1_/chanx_left_out[0] set_disable_timing cbx_4__1_/chanx_right_out[0] -set_disable_timing cbx_4__1_/chanx_right_out[1] +set_disable_timing cbx_4__1_/chanx_left_out[1] set_disable_timing cbx_4__1_/chanx_left_out[2] set_disable_timing cbx_4__1_/chanx_right_out[2] set_disable_timing cbx_4__1_/chanx_left_out[3] @@ -1639,7 +1641,6 @@ set_disable_timing cbx_4__2_/chanx_right_in[2] set_disable_timing cbx_4__2_/chanx_left_in[3] set_disable_timing cbx_4__2_/chanx_right_in[3] set_disable_timing cbx_4__2_/chanx_left_in[4] -set_disable_timing cbx_4__2_/chanx_right_in[4] set_disable_timing cbx_4__2_/chanx_left_in[5] set_disable_timing cbx_4__2_/chanx_right_in[5] set_disable_timing cbx_4__2_/chanx_left_in[6] @@ -1659,7 +1660,6 @@ set_disable_timing cbx_4__2_/chanx_right_out[2] set_disable_timing cbx_4__2_/chanx_left_out[3] set_disable_timing cbx_4__2_/chanx_right_out[3] set_disable_timing cbx_4__2_/chanx_left_out[4] -set_disable_timing cbx_4__2_/chanx_right_out[4] set_disable_timing cbx_4__2_/chanx_left_out[5] set_disable_timing cbx_4__2_/chanx_right_out[5] set_disable_timing cbx_4__2_/chanx_left_out[6] @@ -1710,7 +1710,6 @@ set_disable_timing cbx_4__3_/chanx_right_in[3] set_disable_timing cbx_4__3_/chanx_left_in[4] set_disable_timing cbx_4__3_/chanx_right_in[4] set_disable_timing cbx_4__3_/chanx_left_in[5] -set_disable_timing cbx_4__3_/chanx_right_in[5] set_disable_timing cbx_4__3_/chanx_left_in[6] set_disable_timing cbx_4__3_/chanx_right_in[6] set_disable_timing cbx_4__3_/chanx_left_in[7] @@ -1730,7 +1729,6 @@ set_disable_timing cbx_4__3_/chanx_right_out[3] set_disable_timing cbx_4__3_/chanx_left_out[4] set_disable_timing cbx_4__3_/chanx_right_out[4] set_disable_timing cbx_4__3_/chanx_left_out[5] -set_disable_timing cbx_4__3_/chanx_right_out[5] set_disable_timing cbx_4__3_/chanx_left_out[6] set_disable_timing cbx_4__3_/chanx_right_out[6] set_disable_timing cbx_4__3_/chanx_left_out[7] @@ -1744,7 +1742,6 @@ set_disable_timing cbx_4__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6 set_disable_timing cbx_4__3_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] set_disable_timing cbx_4__3_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] set_disable_timing cbx_4__3_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] -set_disable_timing cbx_4__3_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[1] set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[0] set_disable_timing cbx_4__3_/mux_bottom_ipin_1/in[1] @@ -1758,7 +1755,6 @@ set_disable_timing cbx_4__3_/mux_top_ipin_1/in[0] set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[3] set_disable_timing cbx_4__3_/mux_top_ipin_2/in[1] set_disable_timing cbx_4__3_/mux_bottom_ipin_0/in[2] -set_disable_timing cbx_4__3_/mux_top_ipin_2/in[0] set_disable_timing cbx_4__3_/mux_bottom_ipin_2/in[3] set_disable_timing cbx_4__3_/mux_bottom_ipin_2/in[2] set_disable_timing cbx_4__3_/mux_top_ipin_0/in[3] @@ -2350,7 +2346,6 @@ set_disable_timing cby_1__2_/mux_right_ipin_0/in[2] ################################################## # Disable timing for Connection block cby_1__1_ ################################################## -set_disable_timing cby_1__3_/chany_bottom_in[0] set_disable_timing cby_1__3_/chany_top_in[0] set_disable_timing cby_1__3_/chany_bottom_in[1] set_disable_timing cby_1__3_/chany_top_in[1] @@ -2370,7 +2365,6 @@ set_disable_timing cby_1__3_/chany_bottom_in[8] set_disable_timing cby_1__3_/chany_top_in[8] set_disable_timing cby_1__3_/chany_bottom_in[9] set_disable_timing cby_1__3_/chany_top_in[9] -set_disable_timing cby_1__3_/chany_bottom_out[0] set_disable_timing cby_1__3_/chany_top_out[0] set_disable_timing cby_1__3_/chany_bottom_out[1] set_disable_timing cby_1__3_/chany_top_out[1] @@ -2414,12 +2408,12 @@ set_disable_timing cby_1__3_/mux_right_ipin_0/in[2] ################################################## set_disable_timing cby_1__4_/chany_bottom_in[0] set_disable_timing cby_1__4_/chany_top_in[0] -set_disable_timing cby_1__4_/chany_bottom_in[1] set_disable_timing cby_1__4_/chany_top_in[1] set_disable_timing cby_1__4_/chany_bottom_in[2] set_disable_timing cby_1__4_/chany_top_in[2] set_disable_timing cby_1__4_/chany_bottom_in[3] set_disable_timing cby_1__4_/chany_top_in[3] +set_disable_timing cby_1__4_/chany_bottom_in[4] set_disable_timing cby_1__4_/chany_top_in[4] set_disable_timing cby_1__4_/chany_bottom_in[5] set_disable_timing cby_1__4_/chany_top_in[5] @@ -2433,12 +2427,12 @@ set_disable_timing cby_1__4_/chany_bottom_in[9] set_disable_timing cby_1__4_/chany_top_in[9] set_disable_timing cby_1__4_/chany_bottom_out[0] set_disable_timing cby_1__4_/chany_top_out[0] -set_disable_timing cby_1__4_/chany_bottom_out[1] set_disable_timing cby_1__4_/chany_top_out[1] set_disable_timing cby_1__4_/chany_bottom_out[2] set_disable_timing cby_1__4_/chany_top_out[2] set_disable_timing cby_1__4_/chany_bottom_out[3] set_disable_timing cby_1__4_/chany_top_out[3] +set_disable_timing cby_1__4_/chany_bottom_out[4] set_disable_timing cby_1__4_/chany_top_out[4] set_disable_timing cby_1__4_/chany_bottom_out[5] set_disable_timing cby_1__4_/chany_top_out[5] @@ -2482,6 +2476,7 @@ set_disable_timing cby_2__1_/chany_bottom_in[3] set_disable_timing cby_2__1_/chany_top_in[3] set_disable_timing cby_2__1_/chany_bottom_in[4] set_disable_timing cby_2__1_/chany_top_in[4] +set_disable_timing cby_2__1_/chany_bottom_in[5] set_disable_timing cby_2__1_/chany_top_in[5] set_disable_timing cby_2__1_/chany_bottom_in[6] set_disable_timing cby_2__1_/chany_top_in[6] @@ -2501,6 +2496,7 @@ set_disable_timing cby_2__1_/chany_bottom_out[3] set_disable_timing cby_2__1_/chany_top_out[3] set_disable_timing cby_2__1_/chany_bottom_out[4] set_disable_timing cby_2__1_/chany_top_out[4] +set_disable_timing cby_2__1_/chany_bottom_out[5] set_disable_timing cby_2__1_/chany_top_out[5] set_disable_timing cby_2__1_/chany_bottom_out[6] set_disable_timing cby_2__1_/chany_top_out[6] @@ -2544,6 +2540,7 @@ set_disable_timing cby_2__2_/chany_bottom_in[4] set_disable_timing cby_2__2_/chany_top_in[4] set_disable_timing cby_2__2_/chany_bottom_in[5] set_disable_timing cby_2__2_/chany_top_in[5] +set_disable_timing cby_2__2_/chany_bottom_in[6] set_disable_timing cby_2__2_/chany_top_in[6] set_disable_timing cby_2__2_/chany_bottom_in[7] set_disable_timing cby_2__2_/chany_top_in[7] @@ -2563,6 +2560,7 @@ set_disable_timing cby_2__2_/chany_bottom_out[4] set_disable_timing cby_2__2_/chany_top_out[4] set_disable_timing cby_2__2_/chany_bottom_out[5] set_disable_timing cby_2__2_/chany_top_out[5] +set_disable_timing cby_2__2_/chany_bottom_out[6] set_disable_timing cby_2__2_/chany_top_out[6] set_disable_timing cby_2__2_/chany_bottom_out[7] set_disable_timing cby_2__2_/chany_top_out[7] @@ -2606,6 +2604,7 @@ set_disable_timing cby_2__3_/chany_bottom_in[5] set_disable_timing cby_2__3_/chany_top_in[5] set_disable_timing cby_2__3_/chany_bottom_in[6] set_disable_timing cby_2__3_/chany_top_in[6] +set_disable_timing cby_2__3_/chany_bottom_in[7] set_disable_timing cby_2__3_/chany_top_in[7] set_disable_timing cby_2__3_/chany_bottom_in[8] set_disable_timing cby_2__3_/chany_top_in[8] @@ -2625,6 +2624,7 @@ set_disable_timing cby_2__3_/chany_bottom_out[5] set_disable_timing cby_2__3_/chany_top_out[5] set_disable_timing cby_2__3_/chany_bottom_out[6] set_disable_timing cby_2__3_/chany_top_out[6] +set_disable_timing cby_2__3_/chany_bottom_out[7] set_disable_timing cby_2__3_/chany_top_out[7] set_disable_timing cby_2__3_/chany_bottom_out[8] set_disable_timing cby_2__3_/chany_top_out[8] @@ -2714,6 +2714,7 @@ set_disable_timing cby_2__4_/mux_right_ipin_0/in[2] ################################################## # Disable timing for Connection block cby_1__1_ ################################################## +set_disable_timing cby_3__1_/chany_bottom_in[0] set_disable_timing cby_3__1_/chany_top_in[0] set_disable_timing cby_3__1_/chany_bottom_in[1] set_disable_timing cby_3__1_/chany_top_in[1] @@ -2733,6 +2734,7 @@ set_disable_timing cby_3__1_/chany_bottom_in[8] set_disable_timing cby_3__1_/chany_top_in[8] set_disable_timing cby_3__1_/chany_bottom_in[9] set_disable_timing cby_3__1_/chany_top_in[9] +set_disable_timing cby_3__1_/chany_bottom_out[0] set_disable_timing cby_3__1_/chany_top_out[0] set_disable_timing cby_3__1_/chany_bottom_out[1] set_disable_timing cby_3__1_/chany_top_out[1] @@ -2775,6 +2777,7 @@ set_disable_timing cby_3__1_/mux_right_ipin_0/in[2] # Disable timing for Connection block cby_1__1_ ################################################## set_disable_timing cby_3__2_/chany_top_in[0] +set_disable_timing cby_3__2_/chany_bottom_in[1] set_disable_timing cby_3__2_/chany_top_in[1] set_disable_timing cby_3__2_/chany_bottom_in[2] set_disable_timing cby_3__2_/chany_top_in[2] @@ -2793,6 +2796,7 @@ set_disable_timing cby_3__2_/chany_top_in[8] set_disable_timing cby_3__2_/chany_bottom_in[9] set_disable_timing cby_3__2_/chany_top_in[9] set_disable_timing cby_3__2_/chany_top_out[0] +set_disable_timing cby_3__2_/chany_bottom_out[1] set_disable_timing cby_3__2_/chany_top_out[1] set_disable_timing cby_3__2_/chany_bottom_out[2] set_disable_timing cby_3__2_/chany_top_out[2] @@ -2835,6 +2839,7 @@ set_disable_timing cby_3__2_/mux_right_ipin_0/in[2] set_disable_timing cby_3__3_/chany_bottom_in[0] set_disable_timing cby_3__3_/chany_top_in[0] set_disable_timing cby_3__3_/chany_top_in[1] +set_disable_timing cby_3__3_/chany_bottom_in[2] set_disable_timing cby_3__3_/chany_top_in[2] set_disable_timing cby_3__3_/chany_bottom_in[3] set_disable_timing cby_3__3_/chany_top_in[3] @@ -2853,6 +2858,7 @@ set_disable_timing cby_3__3_/chany_top_in[9] set_disable_timing cby_3__3_/chany_bottom_out[0] set_disable_timing cby_3__3_/chany_top_out[0] set_disable_timing cby_3__3_/chany_top_out[1] +set_disable_timing cby_3__3_/chany_bottom_out[2] set_disable_timing cby_3__3_/chany_top_out[2] set_disable_timing cby_3__3_/chany_bottom_out[3] set_disable_timing cby_3__3_/chany_top_out[3] @@ -2869,13 +2875,11 @@ set_disable_timing cby_3__3_/chany_top_out[8] set_disable_timing cby_3__3_/chany_bottom_out[9] set_disable_timing cby_3__3_/chany_top_out[9] set_disable_timing cby_3__3_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] -set_disable_timing cby_3__3_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] set_disable_timing cby_3__3_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] set_disable_timing cby_3__3_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] set_disable_timing cby_3__3_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] set_disable_timing cby_3__3_/mux_left_ipin_0/in[1] set_disable_timing cby_3__3_/mux_left_ipin_0/in[0] -set_disable_timing cby_3__3_/mux_left_ipin_1/in[1] set_disable_timing cby_3__3_/mux_left_ipin_1/in[0] set_disable_timing cby_3__3_/mux_right_ipin_0/in[1] set_disable_timing cby_3__3_/mux_right_ipin_0/in[0] @@ -2895,6 +2899,7 @@ set_disable_timing cby_3__4_/chany_top_in[0] set_disable_timing cby_3__4_/chany_bottom_in[1] set_disable_timing cby_3__4_/chany_top_in[1] set_disable_timing cby_3__4_/chany_top_in[2] +set_disable_timing cby_3__4_/chany_bottom_in[3] set_disable_timing cby_3__4_/chany_top_in[3] set_disable_timing cby_3__4_/chany_bottom_in[4] set_disable_timing cby_3__4_/chany_top_in[4] @@ -2913,6 +2918,7 @@ set_disable_timing cby_3__4_/chany_top_out[0] set_disable_timing cby_3__4_/chany_bottom_out[1] set_disable_timing cby_3__4_/chany_top_out[1] set_disable_timing cby_3__4_/chany_top_out[2] +set_disable_timing cby_3__4_/chany_bottom_out[3] set_disable_timing cby_3__4_/chany_top_out[3] set_disable_timing cby_3__4_/chany_bottom_out[4] set_disable_timing cby_3__4_/chany_top_out[4] @@ -2954,7 +2960,6 @@ set_disable_timing cby_4__1_/chany_bottom_in[1] set_disable_timing cby_4__1_/chany_top_in[1] set_disable_timing cby_4__1_/chany_bottom_in[2] set_disable_timing cby_4__1_/chany_top_in[2] -set_disable_timing cby_4__1_/chany_bottom_in[3] set_disable_timing cby_4__1_/chany_top_in[3] set_disable_timing cby_4__1_/chany_bottom_in[4] set_disable_timing cby_4__1_/chany_top_in[4] @@ -2974,7 +2979,6 @@ set_disable_timing cby_4__1_/chany_bottom_out[1] set_disable_timing cby_4__1_/chany_top_out[1] set_disable_timing cby_4__1_/chany_bottom_out[2] set_disable_timing cby_4__1_/chany_top_out[2] -set_disable_timing cby_4__1_/chany_bottom_out[3] set_disable_timing cby_4__1_/chany_top_out[3] set_disable_timing cby_4__1_/chany_bottom_out[4] set_disable_timing cby_4__1_/chany_top_out[4] @@ -3061,7 +3065,6 @@ set_disable_timing cby_4__2_/chany_top_in[7] set_disable_timing cby_4__2_/chany_bottom_in[8] set_disable_timing cby_4__2_/chany_top_in[8] set_disable_timing cby_4__2_/chany_bottom_in[9] -set_disable_timing cby_4__2_/chany_top_in[9] set_disable_timing cby_4__2_/chany_bottom_out[0] set_disable_timing cby_4__2_/chany_top_out[0] set_disable_timing cby_4__2_/chany_bottom_out[1] @@ -3081,7 +3084,6 @@ set_disable_timing cby_4__2_/chany_top_out[7] set_disable_timing cby_4__2_/chany_bottom_out[8] set_disable_timing cby_4__2_/chany_top_out[8] set_disable_timing cby_4__2_/chany_bottom_out[9] -set_disable_timing cby_4__2_/chany_top_out[9] set_disable_timing cby_4__2_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] set_disable_timing cby_4__2_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cby_4__2_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] @@ -3151,9 +3153,7 @@ set_disable_timing cby_4__3_/chany_top_in[5] set_disable_timing cby_4__3_/chany_bottom_in[6] set_disable_timing cby_4__3_/chany_top_in[6] set_disable_timing cby_4__3_/chany_bottom_in[7] -set_disable_timing cby_4__3_/chany_top_in[7] set_disable_timing cby_4__3_/chany_bottom_in[8] -set_disable_timing cby_4__3_/chany_top_in[8] set_disable_timing cby_4__3_/chany_bottom_in[9] set_disable_timing cby_4__3_/chany_top_in[9] set_disable_timing cby_4__3_/chany_bottom_out[0] @@ -3171,9 +3171,7 @@ set_disable_timing cby_4__3_/chany_top_out[5] set_disable_timing cby_4__3_/chany_bottom_out[6] set_disable_timing cby_4__3_/chany_top_out[6] set_disable_timing cby_4__3_/chany_bottom_out[7] -set_disable_timing cby_4__3_/chany_top_out[7] set_disable_timing cby_4__3_/chany_bottom_out[8] -set_disable_timing cby_4__3_/chany_top_out[8] set_disable_timing cby_4__3_/chany_bottom_out[9] set_disable_timing cby_4__3_/chany_top_out[9] set_disable_timing cby_4__3_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] @@ -3243,7 +3241,6 @@ set_disable_timing cby_4__4_/chany_top_in[4] set_disable_timing cby_4__4_/chany_bottom_in[5] set_disable_timing cby_4__4_/chany_top_in[5] set_disable_timing cby_4__4_/chany_bottom_in[6] -set_disable_timing cby_4__4_/chany_top_in[6] set_disable_timing cby_4__4_/chany_bottom_in[7] set_disable_timing cby_4__4_/chany_top_in[7] set_disable_timing cby_4__4_/chany_bottom_in[8] @@ -3263,7 +3260,6 @@ set_disable_timing cby_4__4_/chany_top_out[4] set_disable_timing cby_4__4_/chany_bottom_out[5] set_disable_timing cby_4__4_/chany_top_out[5] set_disable_timing cby_4__4_/chany_bottom_out[6] -set_disable_timing cby_4__4_/chany_top_out[6] set_disable_timing cby_4__4_/chany_bottom_out[7] set_disable_timing cby_4__4_/chany_top_out[7] set_disable_timing cby_4__4_/chany_bottom_out[8] @@ -3602,7 +3598,6 @@ set_disable_timing sb_0__2_/chanx_right_in[0] set_disable_timing sb_0__2_/chanx_right_out[1] set_disable_timing sb_0__2_/chanx_right_in[1] set_disable_timing sb_0__2_/chanx_right_out[2] -set_disable_timing sb_0__2_/chanx_right_in[2] set_disable_timing sb_0__2_/chanx_right_out[3] set_disable_timing sb_0__2_/chanx_right_in[3] set_disable_timing sb_0__2_/chanx_right_out[4] @@ -3612,7 +3607,6 @@ set_disable_timing sb_0__2_/chanx_right_in[5] set_disable_timing sb_0__2_/chanx_right_out[6] set_disable_timing sb_0__2_/chanx_right_in[6] set_disable_timing sb_0__2_/chanx_right_out[7] -set_disable_timing sb_0__2_/chanx_right_in[7] set_disable_timing sb_0__2_/chanx_right_out[8] set_disable_timing sb_0__2_/chanx_right_in[8] set_disable_timing sb_0__2_/chanx_right_out[9] @@ -4025,6 +4019,7 @@ set_disable_timing sb_1__0_/chanx_right_in[7] set_disable_timing sb_1__0_/chanx_right_out[8] set_disable_timing sb_1__0_/chanx_right_in[8] set_disable_timing sb_1__0_/chanx_right_out[9] +set_disable_timing sb_1__0_/chanx_right_in[9] set_disable_timing sb_1__0_/chanx_left_in[0] set_disable_timing sb_1__0_/chanx_left_out[0] set_disable_timing sb_1__0_/chanx_left_in[1] @@ -4165,7 +4160,6 @@ set_disable_timing sb_1__1_/chanx_right_in[1] set_disable_timing sb_1__1_/chanx_right_out[2] set_disable_timing sb_1__1_/chanx_right_in[2] set_disable_timing sb_1__1_/chanx_right_out[3] -set_disable_timing sb_1__1_/chanx_right_in[3] set_disable_timing sb_1__1_/chanx_right_out[4] set_disable_timing sb_1__1_/chanx_right_in[4] set_disable_timing sb_1__1_/chanx_right_out[5] @@ -4345,7 +4339,6 @@ set_disable_timing sb_1__1_/mux_bottom_track_9/in[9] ################################################## # Disable timing for Switch block sb_1__1_ ################################################## -set_disable_timing sb_1__2_/chany_top_out[0] set_disable_timing sb_1__2_/chany_top_in[0] set_disable_timing sb_1__2_/chany_top_out[1] set_disable_timing sb_1__2_/chany_top_in[1] @@ -4368,7 +4361,6 @@ set_disable_timing sb_1__2_/chany_top_in[9] set_disable_timing sb_1__2_/chanx_right_out[0] set_disable_timing sb_1__2_/chanx_right_in[0] set_disable_timing sb_1__2_/chanx_right_out[1] -set_disable_timing sb_1__2_/chanx_right_in[1] set_disable_timing sb_1__2_/chanx_right_out[2] set_disable_timing sb_1__2_/chanx_right_in[2] set_disable_timing sb_1__2_/chanx_right_out[3] @@ -4378,12 +4370,12 @@ set_disable_timing sb_1__2_/chanx_right_in[4] set_disable_timing sb_1__2_/chanx_right_out[5] set_disable_timing sb_1__2_/chanx_right_in[5] set_disable_timing sb_1__2_/chanx_right_out[6] -set_disable_timing sb_1__2_/chanx_right_in[6] set_disable_timing sb_1__2_/chanx_right_out[7] set_disable_timing sb_1__2_/chanx_right_in[7] set_disable_timing sb_1__2_/chanx_right_out[8] set_disable_timing sb_1__2_/chanx_right_in[8] set_disable_timing sb_1__2_/chanx_right_out[9] +set_disable_timing sb_1__2_/chanx_right_in[9] set_disable_timing sb_1__2_/chany_bottom_in[0] set_disable_timing sb_1__2_/chany_bottom_out[0] set_disable_timing sb_1__2_/chany_bottom_in[1] @@ -4409,7 +4401,6 @@ set_disable_timing sb_1__2_/chanx_left_out[0] set_disable_timing sb_1__2_/chanx_left_in[1] set_disable_timing sb_1__2_/chanx_left_out[1] set_disable_timing sb_1__2_/chanx_left_in[2] -set_disable_timing sb_1__2_/chanx_left_out[2] set_disable_timing sb_1__2_/chanx_left_in[3] set_disable_timing sb_1__2_/chanx_left_out[3] set_disable_timing sb_1__2_/chanx_left_in[4] @@ -4419,7 +4410,6 @@ set_disable_timing sb_1__2_/chanx_left_out[5] set_disable_timing sb_1__2_/chanx_left_in[6] set_disable_timing sb_1__2_/chanx_left_out[6] set_disable_timing sb_1__2_/chanx_left_in[7] -set_disable_timing sb_1__2_/chanx_left_out[7] set_disable_timing sb_1__2_/chanx_left_in[8] set_disable_timing sb_1__2_/chanx_left_out[8] set_disable_timing sb_1__2_/chanx_left_in[9] @@ -4470,7 +4460,6 @@ set_disable_timing sb_1__2_/mux_left_track_9/in[2] set_disable_timing sb_1__2_/mux_top_track_16/in[0] set_disable_timing sb_1__2_/mux_bottom_track_9/in[2] set_disable_timing sb_1__2_/mux_left_track_1/in[4] -set_disable_timing sb_1__2_/mux_top_track_0/in[1] set_disable_timing sb_1__2_/mux_bottom_track_1/in[3] set_disable_timing sb_1__2_/mux_left_track_9/in[3] set_disable_timing sb_1__2_/mux_top_track_8/in[1] @@ -4553,12 +4542,12 @@ set_disable_timing sb_1__2_/mux_bottom_track_9/in[9] ################################################## set_disable_timing sb_1__3_/chany_top_out[0] set_disable_timing sb_1__3_/chany_top_in[0] -set_disable_timing sb_1__3_/chany_top_out[1] set_disable_timing sb_1__3_/chany_top_in[1] set_disable_timing sb_1__3_/chany_top_out[2] set_disable_timing sb_1__3_/chany_top_in[2] set_disable_timing sb_1__3_/chany_top_out[3] set_disable_timing sb_1__3_/chany_top_in[3] +set_disable_timing sb_1__3_/chany_top_out[4] set_disable_timing sb_1__3_/chany_top_in[4] set_disable_timing sb_1__3_/chany_top_out[5] set_disable_timing sb_1__3_/chany_top_in[5] @@ -4585,11 +4574,10 @@ set_disable_timing sb_1__3_/chanx_right_in[5] set_disable_timing sb_1__3_/chanx_right_out[6] set_disable_timing sb_1__3_/chanx_right_in[6] set_disable_timing sb_1__3_/chanx_right_out[7] -set_disable_timing sb_1__3_/chanx_right_in[7] set_disable_timing sb_1__3_/chanx_right_out[8] set_disable_timing sb_1__3_/chanx_right_in[8] set_disable_timing sb_1__3_/chanx_right_out[9] -set_disable_timing sb_1__3_/chany_bottom_in[0] +set_disable_timing sb_1__3_/chanx_right_in[9] set_disable_timing sb_1__3_/chany_bottom_out[0] set_disable_timing sb_1__3_/chany_bottom_in[1] set_disable_timing sb_1__3_/chany_bottom_out[1] @@ -4697,6 +4685,7 @@ set_disable_timing sb_1__3_/mux_bottom_track_1/in[5] set_disable_timing sb_1__3_/mux_top_track_16/in[3] set_disable_timing sb_1__3_/mux_bottom_track_9/in[5] set_disable_timing sb_1__3_/mux_left_track_1/in[6] +set_disable_timing sb_1__3_/mux_top_track_8/in[3] set_disable_timing sb_1__3_/mux_bottom_track_17/in[4] set_disable_timing sb_1__3_/mux_top_track_0/in[4] set_disable_timing sb_1__3_/mux_right_track_8/in[5] @@ -4776,12 +4765,12 @@ set_disable_timing sb_1__4_/chanx_right_out[9] set_disable_timing sb_1__4_/chanx_right_in[9] set_disable_timing sb_1__4_/chany_bottom_in[0] set_disable_timing sb_1__4_/chany_bottom_out[0] -set_disable_timing sb_1__4_/chany_bottom_in[1] set_disable_timing sb_1__4_/chany_bottom_out[1] set_disable_timing sb_1__4_/chany_bottom_in[2] set_disable_timing sb_1__4_/chany_bottom_out[2] set_disable_timing sb_1__4_/chany_bottom_in[3] set_disable_timing sb_1__4_/chany_bottom_out[3] +set_disable_timing sb_1__4_/chany_bottom_in[4] set_disable_timing sb_1__4_/chany_bottom_out[4] set_disable_timing sb_1__4_/chany_bottom_in[5] set_disable_timing sb_1__4_/chany_bottom_out[5] @@ -4872,12 +4861,12 @@ set_disable_timing sb_1__4_/mux_left_track_1/in[2] set_disable_timing sb_1__4_/mux_bottom_track_13/in[1] set_disable_timing sb_1__4_/mux_right_track_8/in[3] set_disable_timing sb_1__4_/mux_left_track_9/in[2] -set_disable_timing sb_1__4_/mux_right_track_0/in[3] set_disable_timing sb_1__4_/mux_left_track_17/in[2] set_disable_timing sb_1__4_/mux_right_track_16/in[3] set_disable_timing sb_1__4_/mux_left_track_1/in[3] set_disable_timing sb_1__4_/mux_right_track_8/in[4] set_disable_timing sb_1__4_/mux_left_track_9/in[3] +set_disable_timing sb_1__4_/mux_right_track_0/in[4] set_disable_timing sb_1__4_/mux_left_track_17/in[3] set_disable_timing sb_1__4_/mux_right_track_16/in[4] set_disable_timing sb_1__4_/mux_left_track_1/in[4] @@ -4919,6 +4908,7 @@ set_disable_timing sb_2__0_/chany_top_out[3] set_disable_timing sb_2__0_/chany_top_in[3] set_disable_timing sb_2__0_/chany_top_out[4] set_disable_timing sb_2__0_/chany_top_in[4] +set_disable_timing sb_2__0_/chany_top_out[5] set_disable_timing sb_2__0_/chany_top_in[5] set_disable_timing sb_2__0_/chany_top_out[6] set_disable_timing sb_2__0_/chany_top_in[6] @@ -4928,6 +4918,7 @@ set_disable_timing sb_2__0_/chany_top_out[8] set_disable_timing sb_2__0_/chany_top_in[8] set_disable_timing sb_2__0_/chany_top_out[9] set_disable_timing sb_2__0_/chany_top_in[9] +set_disable_timing sb_2__0_/chanx_right_out[0] set_disable_timing sb_2__0_/chanx_right_in[0] set_disable_timing sb_2__0_/chanx_right_out[1] set_disable_timing sb_2__0_/chanx_right_in[1] @@ -4944,6 +4935,7 @@ set_disable_timing sb_2__0_/chanx_right_in[6] set_disable_timing sb_2__0_/chanx_right_out[7] set_disable_timing sb_2__0_/chanx_right_in[7] set_disable_timing sb_2__0_/chanx_right_out[8] +set_disable_timing sb_2__0_/chanx_right_in[8] set_disable_timing sb_2__0_/chanx_right_out[9] set_disable_timing sb_2__0_/chanx_right_in[9] set_disable_timing sb_2__0_/chanx_left_in[0] @@ -4965,15 +4957,18 @@ set_disable_timing sb_2__0_/chanx_left_out[7] set_disable_timing sb_2__0_/chanx_left_in[8] set_disable_timing sb_2__0_/chanx_left_out[8] set_disable_timing sb_2__0_/chanx_left_in[9] +set_disable_timing sb_2__0_/chanx_left_out[9] set_disable_timing sb_2__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_2__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] set_disable_timing sb_2__0_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_2__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_2__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_2__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] @@ -4988,6 +4983,7 @@ set_disable_timing sb_2__0_/mux_top_track_2/in[0] set_disable_timing sb_2__0_/mux_right_track_0/in[3] set_disable_timing sb_2__0_/mux_right_track_8/in[4] set_disable_timing sb_2__0_/mux_right_track_16/in[3] +set_disable_timing sb_2__0_/mux_right_track_0/in[4] set_disable_timing sb_2__0_/mux_right_track_8/in[5] set_disable_timing sb_2__0_/mux_right_track_16/in[4] set_disable_timing sb_2__0_/mux_right_track_0/in[5] @@ -5034,6 +5030,7 @@ set_disable_timing sb_2__0_/mux_left_track_9/in[4] set_disable_timing sb_2__0_/mux_top_track_8/in[0] set_disable_timing sb_2__0_/mux_left_track_17/in[4] set_disable_timing sb_2__0_/mux_top_track_0/in[2] +set_disable_timing sb_2__0_/mux_top_track_10/in[0] set_disable_timing sb_2__0_/mux_left_track_1/in[6] set_disable_timing sb_2__0_/mux_top_track_2/in[2] set_disable_timing sb_2__0_/mux_top_track_0/in[3] @@ -5066,6 +5063,7 @@ set_disable_timing sb_2__1_/chany_top_out[4] set_disable_timing sb_2__1_/chany_top_in[4] set_disable_timing sb_2__1_/chany_top_out[5] set_disable_timing sb_2__1_/chany_top_in[5] +set_disable_timing sb_2__1_/chany_top_out[6] set_disable_timing sb_2__1_/chany_top_in[6] set_disable_timing sb_2__1_/chany_top_out[7] set_disable_timing sb_2__1_/chany_top_in[7] @@ -5073,11 +5071,11 @@ set_disable_timing sb_2__1_/chany_top_out[8] set_disable_timing sb_2__1_/chany_top_in[8] set_disable_timing sb_2__1_/chany_top_out[9] set_disable_timing sb_2__1_/chany_top_in[9] +set_disable_timing sb_2__1_/chanx_right_out[0] set_disable_timing sb_2__1_/chanx_right_in[0] set_disable_timing sb_2__1_/chanx_right_out[1] set_disable_timing sb_2__1_/chanx_right_in[1] set_disable_timing sb_2__1_/chanx_right_out[2] -set_disable_timing sb_2__1_/chanx_right_in[2] set_disable_timing sb_2__1_/chanx_right_out[3] set_disable_timing sb_2__1_/chanx_right_in[3] set_disable_timing sb_2__1_/chanx_right_out[4] @@ -5102,6 +5100,7 @@ set_disable_timing sb_2__1_/chany_bottom_in[3] set_disable_timing sb_2__1_/chany_bottom_out[3] set_disable_timing sb_2__1_/chany_bottom_in[4] set_disable_timing sb_2__1_/chany_bottom_out[4] +set_disable_timing sb_2__1_/chany_bottom_in[5] set_disable_timing sb_2__1_/chany_bottom_out[5] set_disable_timing sb_2__1_/chany_bottom_in[6] set_disable_timing sb_2__1_/chany_bottom_out[6] @@ -5118,7 +5117,6 @@ set_disable_timing sb_2__1_/chanx_left_out[1] set_disable_timing sb_2__1_/chanx_left_in[2] set_disable_timing sb_2__1_/chanx_left_out[2] set_disable_timing sb_2__1_/chanx_left_in[3] -set_disable_timing sb_2__1_/chanx_left_out[3] set_disable_timing sb_2__1_/chanx_left_in[4] set_disable_timing sb_2__1_/chanx_left_out[4] set_disable_timing sb_2__1_/chanx_left_in[5] @@ -5216,6 +5214,7 @@ set_disable_timing sb_2__1_/mux_top_track_0/in[5] set_disable_timing sb_2__1_/mux_right_track_8/in[7] set_disable_timing sb_2__1_/mux_left_track_9/in[7] set_disable_timing sb_2__1_/mux_top_track_8/in[5] +set_disable_timing sb_2__1_/mux_right_track_0/in[5] set_disable_timing sb_2__1_/mux_left_track_17/in[6] set_disable_timing sb_2__1_/mux_top_track_16/in[5] set_disable_timing sb_2__1_/mux_right_track_16/in[4] @@ -5271,13 +5270,13 @@ set_disable_timing sb_2__2_/chany_top_out[5] set_disable_timing sb_2__2_/chany_top_in[5] set_disable_timing sb_2__2_/chany_top_out[6] set_disable_timing sb_2__2_/chany_top_in[6] +set_disable_timing sb_2__2_/chany_top_out[7] set_disable_timing sb_2__2_/chany_top_in[7] set_disable_timing sb_2__2_/chany_top_out[8] set_disable_timing sb_2__2_/chany_top_in[8] set_disable_timing sb_2__2_/chany_top_out[9] set_disable_timing sb_2__2_/chany_top_in[9] set_disable_timing sb_2__2_/chanx_right_out[0] -set_disable_timing sb_2__2_/chanx_right_in[0] set_disable_timing sb_2__2_/chanx_right_out[1] set_disable_timing sb_2__2_/chanx_right_in[1] set_disable_timing sb_2__2_/chanx_right_out[2] @@ -5287,12 +5286,12 @@ set_disable_timing sb_2__2_/chanx_right_in[3] set_disable_timing sb_2__2_/chanx_right_out[4] set_disable_timing sb_2__2_/chanx_right_in[4] set_disable_timing sb_2__2_/chanx_right_out[5] -set_disable_timing sb_2__2_/chanx_right_in[5] set_disable_timing sb_2__2_/chanx_right_out[6] set_disable_timing sb_2__2_/chanx_right_in[6] set_disable_timing sb_2__2_/chanx_right_out[7] set_disable_timing sb_2__2_/chanx_right_in[7] set_disable_timing sb_2__2_/chanx_right_out[8] +set_disable_timing sb_2__2_/chanx_right_in[8] set_disable_timing sb_2__2_/chanx_right_out[9] set_disable_timing sb_2__2_/chanx_right_in[9] set_disable_timing sb_2__2_/chany_bottom_in[0] @@ -5307,6 +5306,7 @@ set_disable_timing sb_2__2_/chany_bottom_in[4] set_disable_timing sb_2__2_/chany_bottom_out[4] set_disable_timing sb_2__2_/chany_bottom_in[5] set_disable_timing sb_2__2_/chany_bottom_out[5] +set_disable_timing sb_2__2_/chany_bottom_in[6] set_disable_timing sb_2__2_/chany_bottom_out[6] set_disable_timing sb_2__2_/chany_bottom_in[7] set_disable_timing sb_2__2_/chany_bottom_out[7] @@ -5317,7 +5317,6 @@ set_disable_timing sb_2__2_/chany_bottom_out[9] set_disable_timing sb_2__2_/chanx_left_in[0] set_disable_timing sb_2__2_/chanx_left_out[0] set_disable_timing sb_2__2_/chanx_left_in[1] -set_disable_timing sb_2__2_/chanx_left_out[1] set_disable_timing sb_2__2_/chanx_left_in[2] set_disable_timing sb_2__2_/chanx_left_out[2] set_disable_timing sb_2__2_/chanx_left_in[3] @@ -5327,12 +5326,12 @@ set_disable_timing sb_2__2_/chanx_left_out[4] set_disable_timing sb_2__2_/chanx_left_in[5] set_disable_timing sb_2__2_/chanx_left_out[5] set_disable_timing sb_2__2_/chanx_left_in[6] -set_disable_timing sb_2__2_/chanx_left_out[6] set_disable_timing sb_2__2_/chanx_left_in[7] set_disable_timing sb_2__2_/chanx_left_out[7] set_disable_timing sb_2__2_/chanx_left_in[8] set_disable_timing sb_2__2_/chanx_left_out[8] set_disable_timing sb_2__2_/chanx_left_in[9] +set_disable_timing sb_2__2_/chanx_left_out[9] set_disable_timing sb_2__2_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_2__2_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] set_disable_timing sb_2__2_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] @@ -5493,10 +5492,10 @@ set_disable_timing sb_2__3_/chanx_right_in[4] set_disable_timing sb_2__3_/chanx_right_out[5] set_disable_timing sb_2__3_/chanx_right_in[5] set_disable_timing sb_2__3_/chanx_right_out[6] -set_disable_timing sb_2__3_/chanx_right_in[6] set_disable_timing sb_2__3_/chanx_right_out[7] set_disable_timing sb_2__3_/chanx_right_in[7] set_disable_timing sb_2__3_/chanx_right_out[8] +set_disable_timing sb_2__3_/chanx_right_in[8] set_disable_timing sb_2__3_/chanx_right_out[9] set_disable_timing sb_2__3_/chanx_right_in[9] set_disable_timing sb_2__3_/chany_bottom_in[0] @@ -5513,6 +5512,7 @@ set_disable_timing sb_2__3_/chany_bottom_in[5] set_disable_timing sb_2__3_/chany_bottom_out[5] set_disable_timing sb_2__3_/chany_bottom_in[6] set_disable_timing sb_2__3_/chany_bottom_out[6] +set_disable_timing sb_2__3_/chany_bottom_in[7] set_disable_timing sb_2__3_/chany_bottom_out[7] set_disable_timing sb_2__3_/chany_bottom_in[8] set_disable_timing sb_2__3_/chany_bottom_out[8] @@ -5533,10 +5533,10 @@ set_disable_timing sb_2__3_/chanx_left_out[5] set_disable_timing sb_2__3_/chanx_left_in[6] set_disable_timing sb_2__3_/chanx_left_out[6] set_disable_timing sb_2__3_/chanx_left_in[7] -set_disable_timing sb_2__3_/chanx_left_out[7] set_disable_timing sb_2__3_/chanx_left_in[8] set_disable_timing sb_2__3_/chanx_left_out[8] set_disable_timing sb_2__3_/chanx_left_in[9] +set_disable_timing sb_2__3_/chanx_left_out[9] set_disable_timing sb_2__3_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_2__3_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] set_disable_timing sb_2__3_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] @@ -5819,6 +5819,7 @@ set_disable_timing sb_2__4_/mux_bottom_track_3/in[2] ################################################## # Disable timing for Switch block sb_1__0_ ################################################## +set_disable_timing sb_3__0_/chany_top_out[0] set_disable_timing sb_3__0_/chany_top_in[0] set_disable_timing sb_3__0_/chany_top_out[1] set_disable_timing sb_3__0_/chany_top_in[1] @@ -5840,6 +5841,7 @@ set_disable_timing sb_3__0_/chany_top_out[9] set_disable_timing sb_3__0_/chany_top_in[9] set_disable_timing sb_3__0_/chanx_right_out[0] set_disable_timing sb_3__0_/chanx_right_in[0] +set_disable_timing sb_3__0_/chanx_right_out[1] set_disable_timing sb_3__0_/chanx_right_in[1] set_disable_timing sb_3__0_/chanx_right_out[2] set_disable_timing sb_3__0_/chanx_right_in[2] @@ -5857,6 +5859,7 @@ set_disable_timing sb_3__0_/chanx_right_out[8] set_disable_timing sb_3__0_/chanx_right_in[8] set_disable_timing sb_3__0_/chanx_right_out[9] set_disable_timing sb_3__0_/chanx_right_in[9] +set_disable_timing sb_3__0_/chanx_left_in[0] set_disable_timing sb_3__0_/chanx_left_out[0] set_disable_timing sb_3__0_/chanx_left_in[1] set_disable_timing sb_3__0_/chanx_left_out[1] @@ -5873,6 +5876,7 @@ set_disable_timing sb_3__0_/chanx_left_out[6] set_disable_timing sb_3__0_/chanx_left_in[7] set_disable_timing sb_3__0_/chanx_left_out[7] set_disable_timing sb_3__0_/chanx_left_in[8] +set_disable_timing sb_3__0_/chanx_left_out[8] set_disable_timing sb_3__0_/chanx_left_in[9] set_disable_timing sb_3__0_/chanx_left_out[9] set_disable_timing sb_3__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] @@ -5889,10 +5893,12 @@ set_disable_timing sb_3__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pi set_disable_timing sb_3__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_[0] +set_disable_timing sb_3__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_3__0_/mux_top_track_0/in[0] set_disable_timing sb_3__0_/mux_top_track_2/in[0] set_disable_timing sb_3__0_/mux_right_track_0/in[3] @@ -5912,6 +5918,7 @@ set_disable_timing sb_3__0_/mux_left_track_9/in[6] set_disable_timing sb_3__0_/mux_left_track_17/in[6] set_disable_timing sb_3__0_/mux_left_track_1/in[9] set_disable_timing sb_3__0_/mux_left_track_9/in[7] +set_disable_timing sb_3__0_/mux_left_track_17/in[7] set_disable_timing sb_3__0_/mux_right_track_8/in[0] set_disable_timing sb_3__0_/mux_left_track_1/in[0] set_disable_timing sb_3__0_/mux_right_track_16/in[0] @@ -5947,6 +5954,7 @@ set_disable_timing sb_3__0_/mux_top_track_0/in[2] set_disable_timing sb_3__0_/mux_top_track_10/in[0] set_disable_timing sb_3__0_/mux_left_track_1/in[6] set_disable_timing sb_3__0_/mux_top_track_2/in[2] +set_disable_timing sb_3__0_/mux_top_track_0/in[3] set_disable_timing sb_3__0_/mux_right_track_0/in[6] set_disable_timing sb_3__0_/mux_top_track_18/in[2] set_disable_timing sb_3__0_/mux_right_track_8/in[7] @@ -5965,6 +5973,7 @@ set_disable_timing sb_3__0_/mux_top_track_16/in[1] # Disable timing for Switch block sb_1__1_ ################################################## set_disable_timing sb_3__1_/chany_top_in[0] +set_disable_timing sb_3__1_/chany_top_out[1] set_disable_timing sb_3__1_/chany_top_in[1] set_disable_timing sb_3__1_/chany_top_out[2] set_disable_timing sb_3__1_/chany_top_in[2] @@ -5984,7 +5993,7 @@ set_disable_timing sb_3__1_/chany_top_out[9] set_disable_timing sb_3__1_/chany_top_in[9] set_disable_timing sb_3__1_/chanx_right_out[0] set_disable_timing sb_3__1_/chanx_right_in[0] -set_disable_timing sb_3__1_/chanx_right_in[1] +set_disable_timing sb_3__1_/chanx_right_out[1] set_disable_timing sb_3__1_/chanx_right_out[2] set_disable_timing sb_3__1_/chanx_right_in[2] set_disable_timing sb_3__1_/chanx_right_out[3] @@ -6001,6 +6010,7 @@ set_disable_timing sb_3__1_/chanx_right_out[8] set_disable_timing sb_3__1_/chanx_right_in[8] set_disable_timing sb_3__1_/chanx_right_out[9] set_disable_timing sb_3__1_/chanx_right_in[9] +set_disable_timing sb_3__1_/chany_bottom_in[0] set_disable_timing sb_3__1_/chany_bottom_out[0] set_disable_timing sb_3__1_/chany_bottom_in[1] set_disable_timing sb_3__1_/chany_bottom_out[1] @@ -6020,11 +6030,11 @@ set_disable_timing sb_3__1_/chany_bottom_in[8] set_disable_timing sb_3__1_/chany_bottom_out[8] set_disable_timing sb_3__1_/chany_bottom_in[9] set_disable_timing sb_3__1_/chany_bottom_out[9] +set_disable_timing sb_3__1_/chanx_left_in[0] set_disable_timing sb_3__1_/chanx_left_out[0] set_disable_timing sb_3__1_/chanx_left_in[1] set_disable_timing sb_3__1_/chanx_left_out[1] set_disable_timing sb_3__1_/chanx_left_in[2] -set_disable_timing sb_3__1_/chanx_left_out[2] set_disable_timing sb_3__1_/chanx_left_in[3] set_disable_timing sb_3__1_/chanx_left_out[3] set_disable_timing sb_3__1_/chanx_left_in[4] @@ -6039,6 +6049,7 @@ set_disable_timing sb_3__1_/chanx_left_in[8] set_disable_timing sb_3__1_/chanx_left_out[8] set_disable_timing sb_3__1_/chanx_left_in[9] set_disable_timing sb_3__1_/chanx_left_out[9] +set_disable_timing sb_3__1_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_3__1_/top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] set_disable_timing sb_3__1_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_3__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] @@ -6046,6 +6057,7 @@ set_disable_timing sb_3__1_/bottom_right_grid_left_width_0_height_0_subtile_0__p set_disable_timing sb_3__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_3__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_3__1_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] +set_disable_timing sb_3__1_/mux_top_track_0/in[0] set_disable_timing sb_3__1_/mux_top_track_8/in[0] set_disable_timing sb_3__1_/mux_right_track_0/in[3] set_disable_timing sb_3__1_/mux_right_track_8/in[4] @@ -6083,7 +6095,6 @@ set_disable_timing sb_3__1_/mux_left_track_9/in[2] set_disable_timing sb_3__1_/mux_top_track_16/in[0] set_disable_timing sb_3__1_/mux_bottom_track_9/in[2] set_disable_timing sb_3__1_/mux_left_track_1/in[4] -set_disable_timing sb_3__1_/mux_top_track_0/in[1] set_disable_timing sb_3__1_/mux_bottom_track_1/in[3] set_disable_timing sb_3__1_/mux_left_track_9/in[3] set_disable_timing sb_3__1_/mux_top_track_8/in[1] @@ -6167,6 +6178,7 @@ set_disable_timing sb_3__1_/mux_bottom_track_9/in[9] set_disable_timing sb_3__2_/chany_top_out[0] set_disable_timing sb_3__2_/chany_top_in[0] set_disable_timing sb_3__2_/chany_top_in[1] +set_disable_timing sb_3__2_/chany_top_out[2] set_disable_timing sb_3__2_/chany_top_in[2] set_disable_timing sb_3__2_/chany_top_out[3] set_disable_timing sb_3__2_/chany_top_in[3] @@ -6191,7 +6203,6 @@ set_disable_timing sb_3__2_/chanx_right_in[2] set_disable_timing sb_3__2_/chanx_right_out[3] set_disable_timing sb_3__2_/chanx_right_in[3] set_disable_timing sb_3__2_/chanx_right_out[4] -set_disable_timing sb_3__2_/chanx_right_in[4] set_disable_timing sb_3__2_/chanx_right_out[5] set_disable_timing sb_3__2_/chanx_right_in[5] set_disable_timing sb_3__2_/chanx_right_out[6] @@ -6203,6 +6214,7 @@ set_disable_timing sb_3__2_/chanx_right_in[8] set_disable_timing sb_3__2_/chanx_right_out[9] set_disable_timing sb_3__2_/chanx_right_in[9] set_disable_timing sb_3__2_/chany_bottom_out[0] +set_disable_timing sb_3__2_/chany_bottom_in[1] set_disable_timing sb_3__2_/chany_bottom_out[1] set_disable_timing sb_3__2_/chany_bottom_in[2] set_disable_timing sb_3__2_/chany_bottom_out[2] @@ -6221,7 +6233,6 @@ set_disable_timing sb_3__2_/chany_bottom_out[8] set_disable_timing sb_3__2_/chany_bottom_in[9] set_disable_timing sb_3__2_/chany_bottom_out[9] set_disable_timing sb_3__2_/chanx_left_in[0] -set_disable_timing sb_3__2_/chanx_left_out[0] set_disable_timing sb_3__2_/chanx_left_in[1] set_disable_timing sb_3__2_/chanx_left_out[1] set_disable_timing sb_3__2_/chanx_left_in[2] @@ -6231,12 +6242,12 @@ set_disable_timing sb_3__2_/chanx_left_out[3] set_disable_timing sb_3__2_/chanx_left_in[4] set_disable_timing sb_3__2_/chanx_left_out[4] set_disable_timing sb_3__2_/chanx_left_in[5] -set_disable_timing sb_3__2_/chanx_left_out[5] set_disable_timing sb_3__2_/chanx_left_in[6] set_disable_timing sb_3__2_/chanx_left_out[6] set_disable_timing sb_3__2_/chanx_left_in[7] set_disable_timing sb_3__2_/chanx_left_out[7] set_disable_timing sb_3__2_/chanx_left_in[8] +set_disable_timing sb_3__2_/chanx_left_out[8] set_disable_timing sb_3__2_/chanx_left_in[9] set_disable_timing sb_3__2_/chanx_left_out[9] set_disable_timing sb_3__2_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] @@ -6244,6 +6255,7 @@ set_disable_timing sb_3__2_/top_right_grid_left_width_0_height_0_subtile_0__pin_ set_disable_timing sb_3__2_/right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_3__2_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] set_disable_timing sb_3__2_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] +set_disable_timing sb_3__2_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_3__2_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_3__2_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] set_disable_timing sb_3__2_/mux_top_track_0/in[0] @@ -6294,7 +6306,6 @@ set_disable_timing sb_3__2_/mux_top_track_16/in[1] set_disable_timing sb_3__2_/mux_bottom_track_9/in[3] set_disable_timing sb_3__2_/mux_top_track_16/in[2] set_disable_timing sb_3__2_/mux_bottom_track_9/in[4] -set_disable_timing sb_3__2_/mux_left_track_1/in[5] set_disable_timing sb_3__2_/mux_top_track_0/in[2] set_disable_timing sb_3__2_/mux_bottom_track_1/in[4] set_disable_timing sb_3__2_/mux_left_track_9/in[4] @@ -6313,6 +6324,7 @@ set_disable_timing sb_3__2_/mux_right_track_8/in[5] set_disable_timing sb_3__2_/mux_left_track_9/in[5] set_disable_timing sb_3__2_/mux_top_track_8/in[4] set_disable_timing sb_3__2_/mux_right_track_0/in[4] +set_disable_timing sb_3__2_/mux_left_track_17/in[5] set_disable_timing sb_3__2_/mux_top_track_16/in[4] set_disable_timing sb_3__2_/mux_right_track_16/in[3] set_disable_timing sb_3__2_/mux_left_track_1/in[7] @@ -6369,6 +6381,7 @@ set_disable_timing sb_3__3_/chany_top_in[0] set_disable_timing sb_3__3_/chany_top_out[1] set_disable_timing sb_3__3_/chany_top_in[1] set_disable_timing sb_3__3_/chany_top_in[2] +set_disable_timing sb_3__3_/chany_top_out[3] set_disable_timing sb_3__3_/chany_top_in[3] set_disable_timing sb_3__3_/chany_top_out[4] set_disable_timing sb_3__3_/chany_top_in[4] @@ -6393,7 +6406,6 @@ set_disable_timing sb_3__3_/chanx_right_in[3] set_disable_timing sb_3__3_/chanx_right_out[4] set_disable_timing sb_3__3_/chanx_right_in[4] set_disable_timing sb_3__3_/chanx_right_out[5] -set_disable_timing sb_3__3_/chanx_right_in[5] set_disable_timing sb_3__3_/chanx_right_out[6] set_disable_timing sb_3__3_/chanx_right_in[6] set_disable_timing sb_3__3_/chanx_right_out[7] @@ -6405,6 +6417,7 @@ set_disable_timing sb_3__3_/chanx_right_in[9] set_disable_timing sb_3__3_/chany_bottom_in[0] set_disable_timing sb_3__3_/chany_bottom_out[0] set_disable_timing sb_3__3_/chany_bottom_out[1] +set_disable_timing sb_3__3_/chany_bottom_in[2] set_disable_timing sb_3__3_/chany_bottom_out[2] set_disable_timing sb_3__3_/chany_bottom_in[3] set_disable_timing sb_3__3_/chany_bottom_out[3] @@ -6433,10 +6446,10 @@ set_disable_timing sb_3__3_/chanx_left_out[4] set_disable_timing sb_3__3_/chanx_left_in[5] set_disable_timing sb_3__3_/chanx_left_out[5] set_disable_timing sb_3__3_/chanx_left_in[6] -set_disable_timing sb_3__3_/chanx_left_out[6] set_disable_timing sb_3__3_/chanx_left_in[7] set_disable_timing sb_3__3_/chanx_left_out[7] set_disable_timing sb_3__3_/chanx_left_in[8] +set_disable_timing sb_3__3_/chanx_left_out[8] set_disable_timing sb_3__3_/chanx_left_in[9] set_disable_timing sb_3__3_/chanx_left_out[9] set_disable_timing sb_3__3_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] @@ -6514,6 +6527,7 @@ set_disable_timing sb_3__3_/mux_right_track_8/in[5] set_disable_timing sb_3__3_/mux_left_track_9/in[5] set_disable_timing sb_3__3_/mux_top_track_8/in[4] set_disable_timing sb_3__3_/mux_right_track_0/in[4] +set_disable_timing sb_3__3_/mux_left_track_17/in[5] set_disable_timing sb_3__3_/mux_top_track_16/in[4] set_disable_timing sb_3__3_/mux_right_track_16/in[3] set_disable_timing sb_3__3_/mux_left_track_1/in[7] @@ -6589,6 +6603,7 @@ set_disable_timing sb_3__4_/chany_bottom_out[0] set_disable_timing sb_3__4_/chany_bottom_in[1] set_disable_timing sb_3__4_/chany_bottom_out[1] set_disable_timing sb_3__4_/chany_bottom_out[2] +set_disable_timing sb_3__4_/chany_bottom_in[3] set_disable_timing sb_3__4_/chany_bottom_out[3] set_disable_timing sb_3__4_/chany_bottom_in[4] set_disable_timing sb_3__4_/chany_bottom_out[4] @@ -6724,7 +6739,6 @@ set_disable_timing sb_4__0_/chany_top_out[1] set_disable_timing sb_4__0_/chany_top_in[1] set_disable_timing sb_4__0_/chany_top_out[2] set_disable_timing sb_4__0_/chany_top_in[2] -set_disable_timing sb_4__0_/chany_top_out[3] set_disable_timing sb_4__0_/chany_top_in[3] set_disable_timing sb_4__0_/chany_top_out[4] set_disable_timing sb_4__0_/chany_top_in[4] @@ -6740,6 +6754,7 @@ set_disable_timing sb_4__0_/chany_top_out[9] set_disable_timing sb_4__0_/chany_top_in[9] set_disable_timing sb_4__0_/chanx_left_in[0] set_disable_timing sb_4__0_/chanx_left_out[0] +set_disable_timing sb_4__0_/chanx_left_in[1] set_disable_timing sb_4__0_/chanx_left_out[1] set_disable_timing sb_4__0_/chanx_left_in[2] set_disable_timing sb_4__0_/chanx_left_out[2] @@ -6760,7 +6775,6 @@ set_disable_timing sb_4__0_/chanx_left_out[9] set_disable_timing sb_4__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_4__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] @@ -6778,7 +6792,6 @@ set_disable_timing sb_4__0_/left_bottom_grid_top_width_0_height_0_subtile_7__pin set_disable_timing sb_4__0_/mux_top_track_0/in[0] set_disable_timing sb_4__0_/mux_top_track_2/in[0] set_disable_timing sb_4__0_/mux_top_track_4/in[0] -set_disable_timing sb_4__0_/mux_top_track_6/in[0] set_disable_timing sb_4__0_/mux_top_track_8/in[0] set_disable_timing sb_4__0_/mux_top_track_10/in[0] set_disable_timing sb_4__0_/mux_top_track_12/in[0] @@ -6833,14 +6846,12 @@ set_disable_timing sb_4__1_/chany_top_in[7] set_disable_timing sb_4__1_/chany_top_out[8] set_disable_timing sb_4__1_/chany_top_in[8] set_disable_timing sb_4__1_/chany_top_out[9] -set_disable_timing sb_4__1_/chany_top_in[9] set_disable_timing sb_4__1_/chany_bottom_in[0] set_disable_timing sb_4__1_/chany_bottom_out[0] set_disable_timing sb_4__1_/chany_bottom_in[1] set_disable_timing sb_4__1_/chany_bottom_out[1] set_disable_timing sb_4__1_/chany_bottom_in[2] set_disable_timing sb_4__1_/chany_bottom_out[2] -set_disable_timing sb_4__1_/chany_bottom_in[3] set_disable_timing sb_4__1_/chany_bottom_out[3] set_disable_timing sb_4__1_/chany_bottom_in[4] set_disable_timing sb_4__1_/chany_bottom_out[4] @@ -6856,7 +6867,7 @@ set_disable_timing sb_4__1_/chany_bottom_in[9] set_disable_timing sb_4__1_/chany_bottom_out[9] set_disable_timing sb_4__1_/chanx_left_in[0] set_disable_timing sb_4__1_/chanx_left_out[0] -set_disable_timing sb_4__1_/chanx_left_out[1] +set_disable_timing sb_4__1_/chanx_left_in[1] set_disable_timing sb_4__1_/chanx_left_in[2] set_disable_timing sb_4__1_/chanx_left_out[2] set_disable_timing sb_4__1_/chanx_left_in[3] @@ -6884,7 +6895,6 @@ set_disable_timing sb_4__1_/top_right_grid_left_width_0_height_0_subtile_6__pin_ set_disable_timing sb_4__1_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] -set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_4__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] @@ -6936,7 +6946,6 @@ set_disable_timing sb_4__1_/mux_top_track_8/in[3] set_disable_timing sb_4__1_/mux_left_track_5/in[0] set_disable_timing sb_4__1_/mux_top_track_16/in[3] set_disable_timing sb_4__1_/mux_left_track_7/in[0] -set_disable_timing sb_4__1_/mux_left_track_3/in[1] set_disable_timing sb_4__1_/mux_top_track_0/in[4] set_disable_timing sb_4__1_/mux_left_track_9/in[1] set_disable_timing sb_4__1_/mux_top_track_8/in[4] @@ -6985,9 +6994,7 @@ set_disable_timing sb_4__2_/chany_top_in[5] set_disable_timing sb_4__2_/chany_top_out[6] set_disable_timing sb_4__2_/chany_top_in[6] set_disable_timing sb_4__2_/chany_top_out[7] -set_disable_timing sb_4__2_/chany_top_in[7] set_disable_timing sb_4__2_/chany_top_out[8] -set_disable_timing sb_4__2_/chany_top_in[8] set_disable_timing sb_4__2_/chany_top_out[9] set_disable_timing sb_4__2_/chany_top_in[9] set_disable_timing sb_4__2_/chany_bottom_in[0] @@ -7009,7 +7016,6 @@ set_disable_timing sb_4__2_/chany_bottom_out[7] set_disable_timing sb_4__2_/chany_bottom_in[8] set_disable_timing sb_4__2_/chany_bottom_out[8] set_disable_timing sb_4__2_/chany_bottom_in[9] -set_disable_timing sb_4__2_/chany_bottom_out[9] set_disable_timing sb_4__2_/chanx_left_in[0] set_disable_timing sb_4__2_/chanx_left_out[0] set_disable_timing sb_4__2_/chanx_left_in[1] @@ -7019,7 +7025,6 @@ set_disable_timing sb_4__2_/chanx_left_out[2] set_disable_timing sb_4__2_/chanx_left_in[3] set_disable_timing sb_4__2_/chanx_left_out[3] set_disable_timing sb_4__2_/chanx_left_in[4] -set_disable_timing sb_4__2_/chanx_left_out[4] set_disable_timing sb_4__2_/chanx_left_in[5] set_disable_timing sb_4__2_/chanx_left_out[5] set_disable_timing sb_4__2_/chanx_left_in[6] @@ -7030,7 +7035,6 @@ set_disable_timing sb_4__2_/chanx_left_in[8] set_disable_timing sb_4__2_/chanx_left_out[8] set_disable_timing sb_4__2_/chanx_left_in[9] set_disable_timing sb_4__2_/chanx_left_out[9] -set_disable_timing sb_4__2_/top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_4__2_/top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_4__2_/top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] set_disable_timing sb_4__2_/top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_[0] @@ -7085,7 +7089,6 @@ set_disable_timing sb_4__2_/mux_bottom_track_17/in[1] set_disable_timing sb_4__2_/mux_left_track_11/in[0] set_disable_timing sb_4__2_/mux_left_track_19/in[1] set_disable_timing sb_4__2_/mux_bottom_track_1/in[2] -set_disable_timing sb_4__2_/mux_left_track_9/in[0] set_disable_timing sb_4__2_/mux_left_track_17/in[1] set_disable_timing sb_4__2_/mux_top_track_0/in[3] set_disable_timing sb_4__2_/mux_left_track_3/in[0] @@ -7140,7 +7143,6 @@ set_disable_timing sb_4__3_/chany_top_in[4] set_disable_timing sb_4__3_/chany_top_out[5] set_disable_timing sb_4__3_/chany_top_in[5] set_disable_timing sb_4__3_/chany_top_out[6] -set_disable_timing sb_4__3_/chany_top_in[6] set_disable_timing sb_4__3_/chany_top_out[7] set_disable_timing sb_4__3_/chany_top_in[7] set_disable_timing sb_4__3_/chany_top_out[8] @@ -7162,9 +7164,7 @@ set_disable_timing sb_4__3_/chany_bottom_out[5] set_disable_timing sb_4__3_/chany_bottom_in[6] set_disable_timing sb_4__3_/chany_bottom_out[6] set_disable_timing sb_4__3_/chany_bottom_in[7] -set_disable_timing sb_4__3_/chany_bottom_out[7] set_disable_timing sb_4__3_/chany_bottom_in[8] -set_disable_timing sb_4__3_/chany_bottom_out[8] set_disable_timing sb_4__3_/chany_bottom_in[9] set_disable_timing sb_4__3_/chany_bottom_out[9] set_disable_timing sb_4__3_/chanx_left_in[0] @@ -7178,7 +7178,6 @@ set_disable_timing sb_4__3_/chanx_left_out[3] set_disable_timing sb_4__3_/chanx_left_in[4] set_disable_timing sb_4__3_/chanx_left_out[4] set_disable_timing sb_4__3_/chanx_left_in[5] -set_disable_timing sb_4__3_/chanx_left_out[5] set_disable_timing sb_4__3_/chanx_left_in[6] set_disable_timing sb_4__3_/chanx_left_out[6] set_disable_timing sb_4__3_/chanx_left_in[7] @@ -7194,7 +7193,6 @@ set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_2__pin_ set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] set_disable_timing sb_4__3_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_[0] @@ -7204,7 +7202,6 @@ set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_4__p set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] set_disable_timing sb_4__3_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] -set_disable_timing sb_4__3_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_4__3_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_4__3_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] set_disable_timing sb_4__3_/mux_top_track_0/in[0] @@ -7224,7 +7221,6 @@ set_disable_timing sb_4__3_/mux_bottom_track_9/in[3] set_disable_timing sb_4__3_/mux_bottom_track_17/in[3] set_disable_timing sb_4__3_/mux_bottom_track_1/in[5] set_disable_timing sb_4__3_/mux_bottom_track_9/in[4] -set_disable_timing sb_4__3_/mux_bottom_track_17/in[4] set_disable_timing sb_4__3_/mux_left_track_1/in[2] set_disable_timing sb_4__3_/mux_left_track_3/in[2] set_disable_timing sb_4__3_/mux_bottom_track_1/in[0] @@ -7239,7 +7235,6 @@ set_disable_timing sb_4__3_/mux_left_track_15/in[0] set_disable_timing sb_4__3_/mux_bottom_track_9/in[1] set_disable_timing sb_4__3_/mux_left_track_13/in[0] set_disable_timing sb_4__3_/mux_bottom_track_17/in[1] -set_disable_timing sb_4__3_/mux_left_track_11/in[0] set_disable_timing sb_4__3_/mux_left_track_19/in[1] set_disable_timing sb_4__3_/mux_bottom_track_1/in[2] set_disable_timing sb_4__3_/mux_left_track_9/in[0] @@ -7297,7 +7292,6 @@ set_disable_timing sb_4__4_/chany_bottom_out[4] set_disable_timing sb_4__4_/chany_bottom_in[5] set_disable_timing sb_4__4_/chany_bottom_out[5] set_disable_timing sb_4__4_/chany_bottom_in[6] -set_disable_timing sb_4__4_/chany_bottom_out[6] set_disable_timing sb_4__4_/chany_bottom_in[7] set_disable_timing sb_4__4_/chany_bottom_out[7] set_disable_timing sb_4__4_/chany_bottom_in[8] @@ -7329,7 +7323,6 @@ set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_2__p set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] -set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] set_disable_timing sb_4__4_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_4__4_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_[0] set_disable_timing sb_4__4_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] @@ -7347,7 +7340,6 @@ set_disable_timing sb_4__4_/mux_bottom_track_5/in[0] set_disable_timing sb_4__4_/mux_bottom_track_7/in[0] set_disable_timing sb_4__4_/mux_bottom_track_9/in[0] set_disable_timing sb_4__4_/mux_bottom_track_11/in[0] -set_disable_timing sb_4__4_/mux_bottom_track_13/in[0] set_disable_timing sb_4__4_/mux_bottom_track_15/in[0] set_disable_timing sb_4__4_/mux_bottom_track_17/in[0] set_disable_timing sb_4__4_/mux_left_track_1/in[1] @@ -8047,229 +8039,76 @@ set_disable_timing grid_clb_3__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_ # Disable Timing for grid[3][2] ####################################### ####################################### -# Disable Timing for unused resources in grid[3][2][0] +# Disable Timing for unused grid[3][2][0] ####################################### ####################################### -# Disable unused pins for pb_graph_node clb[0] +# Disable all the ports for pb_graph_node clb[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[4] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[5] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[6] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[7] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[8] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_I[9] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_O[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_O[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_O[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/clb_clk[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/* ####################################### -# Disable unused mux_inputs for pb_graph_node clb[0] +# Disable all the ports for pb_graph_node fle[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[7] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[8] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[9] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//direct_interc_7_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[10] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[11] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[12] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[13] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/* ####################################### -# Disable unused pins for pb_graph_node fle[0] +# Disable all the ports for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_clk[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* ####################################### -# Disable unused mux_inputs for pb_graph_node fle[0] +# Disable all the ports for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_1_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_2_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_3_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_4_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_5_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* ####################################### -# Disable unused pins for pb_graph_node ble4[0] +# Disable all the ports for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* ####################################### -# Disable unused mux_inputs for pb_graph_node ble4[0] +# Disable all the ports for pb_graph_node fle[1] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/* ####################################### -# Disable unused pins for pb_graph_node lut4[0] +# Disable all the ports for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* ####################################### -# Disable unused pins for pb_graph_node ff[0] +# Disable all the ports for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* ####################################### -# Disable unused pins for pb_graph_node fle[1] +# Disable all the ports for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_clk[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* ####################################### -# Disable unused mux_inputs for pb_graph_node fle[1] +# Disable all the ports for pb_graph_node fle[2] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_1_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_2_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_3_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_4_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_5_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_0_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/* ####################################### -# Disable unused pins for pb_graph_node ble4[0] +# Disable all the ports for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* ####################################### -# Disable unused mux_inputs for pb_graph_node ble4[0] +# Disable all the ports for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* ####################################### -# Disable unused pins for pb_graph_node lut4[0] +# Disable all the ports for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* ####################################### -# Disable unused pins for pb_graph_node ff[0] +# Disable all the ports for pb_graph_node fle[3] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/* ####################################### -# Disable unused pins for pb_graph_node fle[2] +# Disable all the ports for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_clk[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* ####################################### -# Disable unused mux_inputs for pb_graph_node fle[2] +# Disable all the ports for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_1_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_2_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_3_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_4_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_5_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_0_/in[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* ####################################### -# Disable unused pins for pb_graph_node ble4[0] +# Disable all the ports for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] -####################################### -# Disable unused mux_inputs for pb_graph_node ble4[0] -####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] -####################################### -# Disable unused pins for pb_graph_node lut4[0] -####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] -####################################### -# Disable unused pins for pb_graph_node ff[0] -####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] -####################################### -# Disable unused pins for pb_graph_node fle[3] -####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_clk[0] -####################################### -# Disable unused mux_inputs for pb_graph_node fle[3] -####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_2_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_3_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_5_/in[0] -####################################### -# Disable unused pins for pb_graph_node ble4[0] -####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] -####################################### -# Disable unused mux_inputs for pb_graph_node ble4[0] -####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] -####################################### -# Disable unused pins for pb_graph_node lut4[0] -####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] -####################################### -# Disable unused pins for pb_graph_node ff[0] -####################################### -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] -set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +set_disable_timing grid_clb_3__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* ####################################### # Disable Timing for grid[3][3] ####################################### @@ -8570,76 +8409,229 @@ set_disable_timing grid_clb_4__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_ # Disable Timing for grid[4][3] ####################################### ####################################### -# Disable Timing for unused grid[4][3][0] +# Disable Timing for unused resources in grid[4][3][0] ####################################### ####################################### -# Disable all the ports for pb_graph_node clb[0] +# Disable unused pins for pb_graph_node clb[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[4] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[5] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[6] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_I[9] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_O[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_O[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_O[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/clb_clk[0] ####################################### -# Disable all the ports for pb_graph_node fle[0] +# Disable unused mux_inputs for pb_graph_node clb[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[8] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[9] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//direct_interc_7_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[10] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[11] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[12] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[13] ####################################### -# Disable all the ports for pb_graph_node ble4[0] +# Disable unused pins for pb_graph_node fle[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_in[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_out[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/fle_clk[0] ####################################### -# Disable all the ports for pb_graph_node lut4[0] +# Disable unused mux_inputs for pb_graph_node fle[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0//direct_interc_0_/in[0] ####################################### -# Disable all the ports for pb_graph_node ff[0] +# Disable unused pins for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] ####################################### -# Disable all the ports for pb_graph_node fle[1] +# Disable unused mux_inputs for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] ####################################### -# Disable all the ports for pb_graph_node ble4[0] +# Disable unused pins for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] ####################################### -# Disable all the ports for pb_graph_node lut4[0] +# Disable unused pins for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] ####################################### -# Disable all the ports for pb_graph_node ff[0] +# Disable unused pins for pb_graph_node fle[1] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_in[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_out[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/fle_clk[0] ####################################### -# Disable all the ports for pb_graph_node fle[2] +# Disable unused mux_inputs for pb_graph_node fle[1] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_1_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_2_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_3_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_4_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_5_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1//direct_interc_0_/in[0] ####################################### -# Disable all the ports for pb_graph_node ble4[0] +# Disable unused pins for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] ####################################### -# Disable all the ports for pb_graph_node lut4[0] +# Disable unused mux_inputs for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] ####################################### -# Disable all the ports for pb_graph_node ff[0] +# Disable unused pins for pb_graph_node lut4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] ####################################### -# Disable all the ports for pb_graph_node fle[3] +# Disable unused pins for pb_graph_node ff[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] ####################################### -# Disable all the ports for pb_graph_node ble4[0] +# Disable unused pins for pb_graph_node fle[2] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_in[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_out[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/fle_clk[0] ####################################### -# Disable all the ports for pb_graph_node lut4[0] +# Disable unused mux_inputs for pb_graph_node fle[2] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_1_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_2_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_3_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_4_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_5_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2//direct_interc_0_/in[0] ####################################### -# Disable all the ports for pb_graph_node ff[0] +# Disable unused pins for pb_graph_node ble4[0] ####################################### -set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/* +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_out[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_0_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_3_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_4_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[3] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_out[0] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] +####################################### +# Disable unused pins for pb_graph_node fle[3] +####################################### +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/fle_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node fle[3] +####################################### +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_2_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_3_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3//direct_interc_5_/in[0] +####################################### +# Disable unused pins for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_in[2] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/ble4_clk[0] +####################################### +# Disable unused mux_inputs for pb_graph_node ble4[0] +####################################### +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_1_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_2_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//direct_interc_5_/in[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0//mux_ble4_out_0/in[0] +####################################### +# Disable unused pins for pb_graph_node lut4[0] +####################################### +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[1] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0/lut4_in[2] +####################################### +# Disable unused pins for pb_graph_node ff[0] +####################################### +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_D[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_Q[0] +set_disable_timing grid_clb_4__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0/ff_clk[0] ####################################### # Disable Timing for grid[4][4] ####################################### @@ -9152,16 +9144,20 @@ set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__5/* ####################################### set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused grid[5][4][6] +# Disable Timing for unused resources in grid[5][4][6] ####################################### ####################################### -# Disable all the ports for pb_graph_node io[0] +# Disable unused pins for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/* +set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/io_outpad[0] ####################################### -# Disable all the ports for pb_graph_node iopad[0] +# Disable unused mux_inputs for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* +set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6//direct_interc_1_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_5__4_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] ####################################### # Disable Timing for unused grid[5][4][7] ####################################### @@ -9381,16 +9377,20 @@ set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__1/* ####################################### set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused grid[5][1][2] +# Disable Timing for unused resources in grid[5][1][2] ####################################### ####################################### -# Disable all the ports for pb_graph_node io[0] +# Disable unused pins for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/* +set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/io_outpad[0] ####################################### -# Disable all the ports for pb_graph_node iopad[0] +# Disable unused mux_inputs for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2//direct_interc_1_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_5__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] ####################################### # Disable Timing for unused grid[5][1][3] ####################################### @@ -9563,20 +9563,16 @@ set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__1/* ####################################### set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused resources in grid[3][0][2] +# Disable Timing for unused grid[3][0][2] ####################################### ####################################### -# Disable unused pins for pb_graph_node io[0] +# Disable all the ports for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__2/io_outpad[0] +set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__2/* ####################################### -# Disable unused mux_inputs for pb_graph_node io[0] +# Disable all the ports for pb_graph_node iopad[0] ####################################### -set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__2//direct_interc_1_/in[0] -####################################### -# Disable unused pins for pb_graph_node iopad[0] -####################################### -set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] +set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* ####################################### # Disable Timing for unused grid[3][0][3] ####################################### @@ -9622,20 +9618,16 @@ set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__6/* ####################################### set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused resources in grid[3][0][7] +# Disable Timing for unused grid[3][0][7] ####################################### ####################################### -# Disable unused pins for pb_graph_node io[0] +# Disable all the ports for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__7/io_outpad[0] +set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__7/* ####################################### -# Disable unused mux_inputs for pb_graph_node io[0] +# Disable all the ports for pb_graph_node iopad[0] ####################################### -set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__7//direct_interc_1_/in[0] -####################################### -# Disable unused pins for pb_graph_node iopad[0] -####################################### -set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] +set_disable_timing grid_io_bottom_3__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* ####################################### # Disable Timing for grid[2][0] ####################################### diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v index 2e6d979ed..737c52a99 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -39,11 +39,11 @@ wire [0:0] clk_fm; // ----- End Connect Global ports of FPGA top module ----- // ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- -// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[79] ----- - assign gfpga_pad_GPIO_PAD_fm[79] = a[0]; +// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[38] ----- + assign gfpga_pad_GPIO_PAD_fm[38] = a[0]; -// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[74] ----- - assign gfpga_pad_GPIO_PAD_fm[74] = b[0]; +// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[58] ----- + assign gfpga_pad_GPIO_PAD_fm[58] = b[0]; // ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[17] ----- assign c[0] = gfpga_pad_GPIO_PAD_fm[17]; @@ -86,7 +86,6 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[35] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[36] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[37] = 1'b0; - assign gfpga_pad_GPIO_PAD_fm[38] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[39] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[40] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[41] = 1'b0; @@ -106,7 +105,6 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[55] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[56] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[57] = 1'b0; - assign gfpga_pad_GPIO_PAD_fm[58] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[59] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[60] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[61] = 1'b0; @@ -122,10 +120,12 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[71] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[72] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[73] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[74] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[75] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[76] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[77] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[78] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[79] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[80] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[81] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[82] = 1'b0; @@ -622,10 +622,10 @@ initial begin force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}}; @@ -650,14 +650,14 @@ initial begin force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b1011; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b0100; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.grid_clb_3__2_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_3__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; force U0_formal_verification.grid_clb_3__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; force U0_formal_verification.grid_clb_3__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; @@ -862,10 +862,10 @@ initial begin force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}}; @@ -890,14 +890,14 @@ initial begin force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b1110; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b0001; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0001; + force U0_formal_verification.grid_clb_4__3_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1110; force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}}; force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}}; force U0_formal_verification.grid_clb_4__4_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}}; @@ -1406,8 +1406,8 @@ initial begin force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_out[0:3] = 4'b0111; + force U0_formal_verification.sb_1__2_.mem_top_track_0.mem_outb[0:3] = 4'b1000; force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__2_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__2_.mem_top_track_16.mem_out[0:3] = {4{1'b0}}; @@ -1432,8 +1432,8 @@ initial begin force U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__3_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__3_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_out[0:3] = 4'b0011; - force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_outb[0:3] = 4'b1100; + force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.sb_1__3_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__3_.mem_top_track_16.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__3_.mem_top_track_16.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__3_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; @@ -1454,8 +1454,8 @@ initial begin force U0_formal_verification.sb_1__3_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__3_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = 4'b0101; - force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = 4'b1010; + force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_out[0:3] = 4'b0011; + force U0_formal_verification.sb_1__4_.mem_right_track_0.mem_outb[0:3] = 4'b1100; force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_1__4_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_1__4_.mem_right_track_16.mem_out[0:3] = {4{1'b0}}; @@ -1492,14 +1492,14 @@ initial begin force U0_formal_verification.sb_2__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_2__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_2__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_out[0:3] = 4'b0101; - force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_outb[0:3] = 4'b1010; + force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.sb_2__0_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__0_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_2__0_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__0_.mem_right_track_16.mem_out[0:3] = {4{1'b0}}; @@ -1516,8 +1516,8 @@ initial begin force U0_formal_verification.sb_2__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_2__1_.mem_top_track_16.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_out[0:3] = 4'b0101; - force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_outb[0:3] = 4'b1010; + force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.sb_2__1_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__1_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_2__1_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__1_.mem_right_track_16.mem_out[0:3] = {4{1'b0}}; @@ -1614,8 +1614,8 @@ initial begin force U0_formal_verification.sb_2__4_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_2__4_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_out[0:2] = 3'b001; - force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_outb[0:2] = 3'b110; + force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_3__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_3__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_3__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; @@ -1636,10 +1636,10 @@ initial begin force U0_formal_verification.sb_3__0_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__0_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__0_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_out[0:3] = 4'b0100; - force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_outb[0:3] = 4'b1011; - force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b0}}; + force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.sb_3__0_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_out[0:3] = 4'b0111; + force U0_formal_verification.sb_3__1_.mem_top_track_0.mem_outb[0:3] = 4'b1000; force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}}; @@ -1680,12 +1680,12 @@ initial begin force U0_formal_verification.sb_3__2_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__2_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_out[0:3] = 4'b0101; + force U0_formal_verification.sb_3__2_.mem_left_track_1.mem_outb[0:3] = 4'b1010; force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__2_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_out[0:3] = 4'b0110; - force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_outb[0:3] = 4'b1001; + force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.sb_3__2_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__3_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__3_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__3_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; @@ -1708,8 +1708,8 @@ initial begin force U0_formal_verification.sb_3__3_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__3_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__3_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_out[0:3] = 4'b0110; - force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_outb[0:3] = 4'b1001; + force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; + force U0_formal_verification.sb_3__3_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__4_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_3__4_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_3__4_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; @@ -1748,8 +1748,8 @@ initial begin force U0_formal_verification.sb_4__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_4__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; @@ -1792,8 +1792,8 @@ initial begin force U0_formal_verification.sb_4__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__1_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_out[0:1] = 2'b01; + force U0_formal_verification.sb_4__1_.mem_left_track_3.mem_outb[0:1] = 2'b10; force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; @@ -1830,8 +1830,8 @@ initial begin force U0_formal_verification.sb_4__2_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__2_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_4__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; @@ -1852,8 +1852,8 @@ initial begin force U0_formal_verification.sb_4__3_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.sb_4__3_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}}; - force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}}; + force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_out[0:3] = 4'b0101; + force U0_formal_verification.sb_4__3_.mem_bottom_track_17.mem_outb[0:3] = 4'b1010; force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__3_.mem_left_track_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__3_.mem_left_track_3.mem_out[0:1] = {2{1'b0}}; @@ -1864,8 +1864,8 @@ initial begin force U0_formal_verification.sb_4__3_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__3_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_4__3_.mem_left_track_11.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__3_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__3_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; @@ -1886,8 +1886,8 @@ initial begin force U0_formal_verification.sb_4__4_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__4_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_4__4_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_4__4_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_4__4_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; @@ -2092,8 +2092,8 @@ initial begin force U0_formal_verification.cbx_3__0_.mem_top_ipin_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_3__0_.mem_top_ipin_7.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_3__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_1.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.cbx_3__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; @@ -2110,8 +2110,8 @@ initial begin force U0_formal_verification.cbx_3__2_.mem_bottom_ipin_1.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.cbx_3__2_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_3__2_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_out[0:2] = 3'b010; - force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_outb[0:2] = 3'b101; + force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cbx_3__2_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_3__2_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_3__2_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_3__2_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}}; @@ -2206,8 +2206,8 @@ initial begin force U0_formal_verification.cbx_4__3_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_4__3_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_out[0:1] = 2'b01; + force U0_formal_verification.cbx_4__3_.mem_top_ipin_2.mem_outb[0:1] = 2'b10; force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_4__4_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}}; @@ -2412,8 +2412,8 @@ initial begin force U0_formal_verification.cby_3__2_.mem_right_ipin_2.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_3__3_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.cby_3__3_.mem_left_ipin_1.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_3__3_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_3__3_.mem_right_ipin_1.mem_out[0:1] = {2{1'b0}}; diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit index d9dd037df..1a79dc354 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -222,7 +222,6 @@ 0 0 1 -0 1 0 0 @@ -623,6 +622,7 @@ 0 0 0 +0 1 1 1 @@ -894,6 +894,8 @@ 0 0 0 +1 +1 0 0 0 @@ -906,6 +908,7 @@ 0 0 0 +1 0 0 0 @@ -918,6 +921,9 @@ 0 0 0 +1 +1 +1 0 0 0 @@ -966,6 +972,7 @@ 0 0 0 +1 0 0 0 @@ -976,9 +983,13 @@ 0 0 0 +1 0 +1 0 +1 0 +1 0 0 0 @@ -1064,6 +1075,7 @@ 0 0 0 +1 0 0 0 @@ -1087,6 +1099,8 @@ 0 0 0 +1 +1 0 0 0 @@ -1097,7 +1111,9 @@ 0 0 0 +1 0 +1 0 0 0 @@ -1262,6 +1278,8 @@ 0 0 0 +1 +1 0 0 0 @@ -1300,12 +1318,6 @@ 0 0 0 -1 -1 -0 -0 -0 -0 0 0 0 @@ -1763,8 +1775,6 @@ 0 0 0 -1 -1 0 0 0 @@ -1969,6 +1979,9 @@ 0 0 0 +1 +1 +1 0 0 0 @@ -2195,10 +2208,6 @@ 0 0 0 -1 -1 -1 -1 0 0 0 @@ -2207,10 +2216,7 @@ 0 0 0 -1 -1 0 -1 0 0 0 @@ -2259,7 +2265,6 @@ 0 0 0 -1 0 0 0 @@ -2270,13 +2275,9 @@ 0 0 0 -1 0 -1 0 -1 0 -1 0 0 0 @@ -2349,7 +2350,6 @@ 0 0 0 -1 0 0 0 @@ -2360,8 +2360,6 @@ 0 0 0 -1 -1 0 0 0 @@ -2369,7 +2367,9 @@ 0 0 0 +1 0 +1 0 0 0 @@ -2600,6 +2600,8 @@ 0 0 0 +1 +1 0 0 0 @@ -2831,6 +2833,7 @@ 0 0 0 +1 0 0 0 @@ -3022,9 +3025,6 @@ 0 0 0 -1 -1 -1 0 0 0 @@ -3072,7 +3072,6 @@ 1 1 1 -1 0 0 0 @@ -3269,9 +3268,10 @@ 0 0 0 -1 0 -1 +0 +0 +0 0 0 0 @@ -3933,8 +3933,8 @@ 0 0 0 -0 -0 +1 +1 0 0 0 @@ -3983,7 +3983,6 @@ 0 0 0 -1 0 0 0 @@ -4016,7 +4015,8 @@ 0 0 0 -1 +0 +0 0 0 1 @@ -4079,17 +4079,17 @@ 0 0 0 -1 0 -1 0 0 0 0 0 0 -1 -1 +0 +0 +0 +0 0 0 0 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml index 09709736b..1ad77e12e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -448,9 +448,9 @@ - + - + @@ -1792,9 +1792,9 @@ - + - + @@ -1820,7 +1820,7 @@ - + @@ -1846,11 +1846,11 @@ - + - + - + @@ -1948,7 +1948,7 @@ - + @@ -1970,19 +1970,19 @@ - + - + - + - + @@ -2154,7 +2154,7 @@ - + @@ -2202,9 +2202,9 @@ - + - + @@ -2226,11 +2226,11 @@ - + - + @@ -2560,9 +2560,9 @@ - + - + @@ -2604,9 +2604,9 @@ - + - + @@ -3530,9 +3530,9 @@ - + - + @@ -3962,11 +3962,11 @@ - + - + - + @@ -4394,13 +4394,13 @@ - + - + - + - + @@ -4418,13 +4418,13 @@ - + - + - + @@ -4522,7 +4522,7 @@ - + @@ -4544,19 +4544,19 @@ - + - + - + - + @@ -4702,7 +4702,7 @@ - + @@ -4724,9 +4724,9 @@ - + - + @@ -4738,11 +4738,11 @@ - + - + @@ -5204,9 +5204,9 @@ - + - + @@ -5670,7 +5670,7 @@ - + @@ -6048,11 +6048,11 @@ - + - + - + @@ -6148,7 +6148,7 @@ - + @@ -6542,11 +6542,11 @@ - + - + @@ -7870,9 +7870,9 @@ - + - + @@ -7970,7 +7970,7 @@ - + @@ -8036,7 +8036,7 @@ - + @@ -8162,11 +8162,11 @@ - + - + @@ -8180,9 +8180,9 @@ - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml index 6cbbd83af..fd78aece6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml @@ -4533,13 +4533,13 @@ - + - + - + - + @@ -4561,16 +4561,12 @@ - - - - - + - + - + @@ -4786,30 +4782,14 @@ - - - - - - - - - - - - - - - - - + - - + + - - + + @@ -4853,30 +4833,14 @@ - - - - - - - - - - - - - - - - - + - - - - - + + + + + @@ -6989,13 +6953,13 @@ - + - + - + - + @@ -7017,12 +6981,16 @@ - + + + + + - + - + @@ -7238,13 +7206,29 @@ - + + + + + + + + + + + + + + + + + - - - - + + + + @@ -7289,14 +7273,30 @@ - + + + + + + + + + + + + + + + + + - + - + @@ -10515,7 +10515,7 @@ - + @@ -10540,7 +10540,7 @@ - + @@ -10744,7 +10744,7 @@ - + @@ -10795,7 +10795,7 @@ - + @@ -11482,7 +11482,7 @@ - + @@ -11793,7 +11793,7 @@ - + @@ -11933,7 +11933,7 @@ - + @@ -12071,7 +12071,7 @@ - + @@ -12083,13 +12083,13 @@ - + - + - - - + + + @@ -12101,8 +12101,8 @@ - - + + @@ -12239,7 +12239,7 @@ - + @@ -12295,8 +12295,8 @@ - - + + @@ -12351,7 +12351,7 @@ - + @@ -12380,7 +12380,7 @@ - + @@ -12407,8 +12407,8 @@ - - + + @@ -12436,7 +12436,7 @@ - + @@ -12444,13 +12444,13 @@ - + - + - - + + @@ -12520,7 +12520,7 @@ - + @@ -12575,7 +12575,7 @@ - + @@ -12630,7 +12630,7 @@ - + @@ -12687,7 +12687,7 @@ - + @@ -12741,8 +12741,8 @@ - - + + @@ -12751,10 +12751,10 @@ - + - - + + @@ -13056,8 +13056,8 @@ - - + + @@ -13141,15 +13141,15 @@ - + - + - - - + + + @@ -13202,20 +13202,20 @@ - + - + - + - + - + @@ -13257,7 +13257,7 @@ - + @@ -13284,7 +13284,7 @@ - + @@ -13390,11 +13390,11 @@ - + - + @@ -13448,20 +13448,20 @@ - + - + - + - + - + @@ -13584,7 +13584,7 @@ - + @@ -13669,10 +13669,10 @@ - + - + @@ -13696,7 +13696,7 @@ - + @@ -13750,12 +13750,12 @@ - + - + - + @@ -13838,7 +13838,7 @@ - + @@ -13864,7 +13864,7 @@ - + @@ -13890,10 +13890,10 @@ - + - + @@ -13947,11 +13947,11 @@ - + - + - + @@ -13976,7 +13976,7 @@ - + @@ -14059,7 +14059,7 @@ - + @@ -14087,7 +14087,7 @@ - + @@ -14117,7 +14117,7 @@ - + @@ -14227,7 +14227,7 @@ - + @@ -14253,7 +14253,7 @@ - + @@ -14283,7 +14283,7 @@ - + @@ -14338,10 +14338,10 @@ - + - + @@ -14709,16 +14709,16 @@ - + - + - + - + @@ -14828,7 +14828,7 @@ - + @@ -14910,7 +14910,7 @@ - + @@ -14963,14 +14963,14 @@ - + - + - + - + @@ -14984,23 +14984,23 @@ - - + + - + - + - + - - + + @@ -15074,7 +15074,7 @@ - + @@ -15100,7 +15100,7 @@ - + @@ -15153,7 +15153,7 @@ - + @@ -15211,7 +15211,7 @@ - + @@ -15265,9 +15265,9 @@ - + - + @@ -15322,7 +15322,7 @@ - + @@ -15351,7 +15351,7 @@ - + @@ -15376,7 +15376,7 @@ - + @@ -15405,7 +15405,7 @@ - + @@ -15434,7 +15434,7 @@ - + @@ -15516,9 +15516,9 @@ - + - + @@ -15572,7 +15572,7 @@ - + @@ -15580,13 +15580,13 @@ - + - + - + - + @@ -15601,7 +15601,7 @@ - + @@ -15629,17 +15629,17 @@ - + - + - + - - + + @@ -15654,7 +15654,7 @@ - + @@ -15685,7 +15685,7 @@ - + @@ -15712,7 +15712,7 @@ - + @@ -15739,7 +15739,7 @@ - + @@ -15795,7 +15795,7 @@ - + @@ -15822,7 +15822,7 @@ - + @@ -15908,7 +15908,7 @@ - + @@ -15934,7 +15934,7 @@ - + @@ -15963,17 +15963,17 @@ - + - + - + - - + + @@ -16017,7 +16017,7 @@ - + @@ -16043,7 +16043,7 @@ - + @@ -16251,7 +16251,7 @@ - + @@ -16278,7 +16278,7 @@ - + @@ -16384,15 +16384,15 @@ - + - + - - - + + + @@ -16715,7 +16715,7 @@ - + @@ -16742,7 +16742,7 @@ - + @@ -16791,7 +16791,7 @@ - + @@ -16836,15 +16836,15 @@ - + - + - + - + @@ -16963,7 +16963,7 @@ - + @@ -17000,7 +17000,7 @@ - + @@ -17082,7 +17082,7 @@ - + @@ -17234,15 +17234,15 @@ - + - + - - - + + + @@ -17325,7 +17325,7 @@ - + @@ -17374,7 +17374,7 @@ - + @@ -17478,23 +17478,23 @@ - + - + - + - + - + - + @@ -17596,15 +17596,15 @@ - + - + - - - + + + @@ -17796,15 +17796,15 @@ - + - + - - - + + + @@ -18406,9 +18406,9 @@ - + - + @@ -18924,7 +18924,7 @@ - + @@ -19029,7 +19029,7 @@ - + @@ -19131,7 +19131,7 @@ - + @@ -19214,7 +19214,7 @@ - + @@ -19276,7 +19276,7 @@ - + @@ -19356,7 +19356,7 @@ - + @@ -19398,7 +19398,7 @@ - + @@ -19666,7 +19666,7 @@ - + @@ -19729,7 +19729,7 @@ - + @@ -19768,7 +19768,7 @@ - + @@ -19834,7 +19834,7 @@ - + @@ -19873,7 +19873,7 @@ - + @@ -19896,18 +19896,18 @@ - + - + - - - - + + + + @@ -19936,7 +19936,7 @@ - + @@ -20019,9 +20019,9 @@ - + - + @@ -20081,14 +20081,14 @@ - + - + - + - + @@ -20121,7 +20121,7 @@ - + @@ -20203,7 +20203,7 @@ - + @@ -20513,7 +20513,7 @@ - + @@ -20615,7 +20615,7 @@ - + @@ -20743,8 +20743,8 @@ - - + + @@ -20926,7 +20926,7 @@ - + @@ -20969,7 +20969,7 @@ - + @@ -21069,14 +21069,14 @@ - + - + - + - + @@ -22350,7 +22350,7 @@ - + @@ -22469,7 +22469,7 @@ - + @@ -22526,7 +22526,7 @@ - + @@ -22548,7 +22548,7 @@ - + @@ -22783,7 +22783,7 @@ - + @@ -22938,7 +22938,7 @@ - + @@ -23036,7 +23036,7 @@ - + @@ -23057,7 +23057,7 @@ - + @@ -23155,15 +23155,15 @@ - + - + - - - + + + @@ -23173,7 +23173,7 @@ - + @@ -23271,7 +23271,7 @@ - + @@ -23292,7 +23292,7 @@ - + @@ -23393,7 +23393,7 @@ - + @@ -23498,7 +23498,7 @@ - + @@ -23644,7 +23644,7 @@ - + @@ -23747,7 +23747,7 @@ - + @@ -23829,7 +23829,7 @@ - + @@ -23850,7 +23850,7 @@ - + @@ -23934,7 +23934,7 @@ - + @@ -23955,7 +23955,7 @@ - + @@ -24035,7 +24035,7 @@ - + @@ -24140,7 +24140,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc index d55c32a26..f87326299 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc @@ -14,7 +14,7 @@ set_units -time s ################################################## # Create clock ################################################## -create_clock -name clk[0] -period 1.565565566e-09 -waveform {0 7.82782783e-10} [get_ports {clk[0]}] +create_clock -name clk[0] -period 1.725112719e-09 -waveform {0 8.625563597e-10} [get_ports {clk[0]}] ################################################## # Create programmable clock ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml index b39a64d74..b9d5872be 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/pin_mapping.xml @@ -3,7 +3,7 @@ --> - - + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index 5d9e929e2..6ed9c4edf 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.809066534 + #0.4880859554 clk[0] <= !clk[0]; end end @@ -106,7 +106,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #11.32693195 + #6.833203316 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 06fd83ed4..2ccec1ac6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -9,20 +9,19 @@ ################################################## # Create clock ################################################## -create_clock clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10} +create_clock clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} ################################################## # Create input and output delays for used I/Os ################################################## -set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[11] -set_input_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[14] -set_output_delay -clock clk[0] -max 1.618133072e-09 gfpga_pad_GPIO_PAD[12] +set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[11] +set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[14] +set_output_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[1] ################################################## # Disable timing for unused I/Os ################################################## set_disable_timing gfpga_pad_GPIO_PAD[0] -set_disable_timing gfpga_pad_GPIO_PAD[1] set_disable_timing gfpga_pad_GPIO_PAD[2] set_disable_timing gfpga_pad_GPIO_PAD[3] set_disable_timing gfpga_pad_GPIO_PAD[4] @@ -32,6 +31,7 @@ set_disable_timing gfpga_pad_GPIO_PAD[7] set_disable_timing gfpga_pad_GPIO_PAD[8] set_disable_timing gfpga_pad_GPIO_PAD[9] set_disable_timing gfpga_pad_GPIO_PAD[10] +set_disable_timing gfpga_pad_GPIO_PAD[12] set_disable_timing gfpga_pad_GPIO_PAD[13] set_disable_timing gfpga_pad_GPIO_PAD[15] set_disable_timing gfpga_pad_GPIO_PAD[16] @@ -156,9 +156,11 @@ set_disable_timing cbx_1__0_/chanx_left_in[7] set_disable_timing cbx_1__0_/chanx_right_in[7] set_disable_timing cbx_1__0_/chanx_left_in[8] set_disable_timing cbx_1__0_/chanx_right_in[8] +set_disable_timing cbx_1__0_/chanx_left_in[9] set_disable_timing cbx_1__0_/chanx_right_in[9] set_disable_timing cbx_1__0_/chanx_left_in[10] set_disable_timing cbx_1__0_/chanx_right_in[10] +set_disable_timing cbx_1__0_/chanx_left_in[11] set_disable_timing cbx_1__0_/chanx_right_in[11] set_disable_timing cbx_1__0_/chanx_left_in[12] set_disable_timing cbx_1__0_/chanx_right_in[12] @@ -180,9 +182,11 @@ set_disable_timing cbx_1__0_/chanx_left_out[7] set_disable_timing cbx_1__0_/chanx_right_out[7] set_disable_timing cbx_1__0_/chanx_left_out[8] set_disable_timing cbx_1__0_/chanx_right_out[8] +set_disable_timing cbx_1__0_/chanx_left_out[9] set_disable_timing cbx_1__0_/chanx_right_out[9] set_disable_timing cbx_1__0_/chanx_left_out[10] set_disable_timing cbx_1__0_/chanx_right_out[10] +set_disable_timing cbx_1__0_/chanx_left_out[11] set_disable_timing cbx_1__0_/chanx_right_out[11] set_disable_timing cbx_1__0_/chanx_left_out[12] set_disable_timing cbx_1__0_/chanx_right_out[12] @@ -272,6 +276,7 @@ set_disable_timing cbx_1__1_/chanx_left_in[1] set_disable_timing cbx_1__1_/chanx_left_in[2] set_disable_timing cbx_1__1_/chanx_right_in[2] set_disable_timing cbx_1__1_/chanx_left_in[3] +set_disable_timing cbx_1__1_/chanx_right_in[3] set_disable_timing cbx_1__1_/chanx_left_in[4] set_disable_timing cbx_1__1_/chanx_right_in[4] set_disable_timing cbx_1__1_/chanx_left_in[5] @@ -296,6 +301,7 @@ set_disable_timing cbx_1__1_/chanx_left_out[1] set_disable_timing cbx_1__1_/chanx_left_out[2] set_disable_timing cbx_1__1_/chanx_right_out[2] set_disable_timing cbx_1__1_/chanx_left_out[3] +set_disable_timing cbx_1__1_/chanx_right_out[3] set_disable_timing cbx_1__1_/chanx_left_out[4] set_disable_timing cbx_1__1_/chanx_right_out[4] set_disable_timing cbx_1__1_/chanx_left_out[5] @@ -315,7 +321,6 @@ set_disable_timing cbx_1__1_/chanx_right_out[11] set_disable_timing cbx_1__1_/chanx_left_out[12] set_disable_timing cbx_1__1_/chanx_right_out[12] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] -set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] @@ -334,7 +339,6 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[0] set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[3] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[1] set_disable_timing cbx_1__1_/mux_top_ipin_0/in[1] -set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[2] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[0] set_disable_timing cbx_1__1_/mux_top_ipin_0/in[0] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[3] @@ -411,9 +415,11 @@ set_disable_timing cby_0__1_/chany_top_in[6] set_disable_timing cby_0__1_/chany_bottom_in[7] set_disable_timing cby_0__1_/chany_top_in[7] set_disable_timing cby_0__1_/chany_bottom_in[8] +set_disable_timing cby_0__1_/chany_top_in[8] set_disable_timing cby_0__1_/chany_bottom_in[9] set_disable_timing cby_0__1_/chany_top_in[9] set_disable_timing cby_0__1_/chany_bottom_in[10] +set_disable_timing cby_0__1_/chany_top_in[10] set_disable_timing cby_0__1_/chany_bottom_in[11] set_disable_timing cby_0__1_/chany_top_in[11] set_disable_timing cby_0__1_/chany_bottom_in[12] @@ -435,9 +441,11 @@ set_disable_timing cby_0__1_/chany_top_out[6] set_disable_timing cby_0__1_/chany_bottom_out[7] set_disable_timing cby_0__1_/chany_top_out[7] set_disable_timing cby_0__1_/chany_bottom_out[8] +set_disable_timing cby_0__1_/chany_top_out[8] set_disable_timing cby_0__1_/chany_bottom_out[9] set_disable_timing cby_0__1_/chany_top_out[9] set_disable_timing cby_0__1_/chany_bottom_out[10] +set_disable_timing cby_0__1_/chany_top_out[10] set_disable_timing cby_0__1_/chany_bottom_out[11] set_disable_timing cby_0__1_/chany_top_out[11] set_disable_timing cby_0__1_/chany_bottom_out[12] @@ -518,9 +526,11 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4] set_disable_timing cby_1__1_/chany_top_in[0] set_disable_timing cby_1__1_/chany_bottom_in[1] set_disable_timing cby_1__1_/chany_top_in[1] +set_disable_timing cby_1__1_/chany_bottom_in[2] set_disable_timing cby_1__1_/chany_top_in[2] set_disable_timing cby_1__1_/chany_bottom_in[3] set_disable_timing cby_1__1_/chany_top_in[3] +set_disable_timing cby_1__1_/chany_bottom_in[4] set_disable_timing cby_1__1_/chany_top_in[4] set_disable_timing cby_1__1_/chany_bottom_in[5] set_disable_timing cby_1__1_/chany_top_in[5] @@ -539,9 +549,11 @@ set_disable_timing cby_1__1_/chany_top_in[12] set_disable_timing cby_1__1_/chany_top_out[0] set_disable_timing cby_1__1_/chany_bottom_out[1] set_disable_timing cby_1__1_/chany_top_out[1] +set_disable_timing cby_1__1_/chany_bottom_out[2] set_disable_timing cby_1__1_/chany_top_out[2] set_disable_timing cby_1__1_/chany_bottom_out[3] set_disable_timing cby_1__1_/chany_top_out[3] +set_disable_timing cby_1__1_/chany_bottom_out[4] set_disable_timing cby_1__1_/chany_top_out[4] set_disable_timing cby_1__1_/chany_bottom_out[5] set_disable_timing cby_1__1_/chany_top_out[5] @@ -561,6 +573,7 @@ set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_out set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] @@ -589,6 +602,7 @@ set_disable_timing cby_1__1_/mux_right_ipin_2/in[1] set_disable_timing cby_1__1_/mux_left_ipin_3/in[2] set_disable_timing cby_1__1_/mux_left_ipin_4/in[0] set_disable_timing cby_1__1_/mux_right_ipin_2/in[0] +set_disable_timing cby_1__1_/mux_left_ipin_4/in[3] set_disable_timing cby_1__1_/mux_left_ipin_5/in[1] set_disable_timing cby_1__1_/mux_left_ipin_4/in[2] set_disable_timing cby_1__1_/mux_left_ipin_5/in[0] @@ -648,9 +662,11 @@ set_disable_timing sb_0__0_/chany_top_in[6] set_disable_timing sb_0__0_/chany_top_out[7] set_disable_timing sb_0__0_/chany_top_in[7] set_disable_timing sb_0__0_/chany_top_out[8] +set_disable_timing sb_0__0_/chany_top_in[8] set_disable_timing sb_0__0_/chany_top_out[9] set_disable_timing sb_0__0_/chany_top_in[9] set_disable_timing sb_0__0_/chany_top_out[10] +set_disable_timing sb_0__0_/chany_top_in[10] set_disable_timing sb_0__0_/chany_top_out[11] set_disable_timing sb_0__0_/chany_top_in[11] set_disable_timing sb_0__0_/chany_top_out[12] @@ -673,9 +689,11 @@ set_disable_timing sb_0__0_/chanx_right_out[7] set_disable_timing sb_0__0_/chanx_right_in[7] set_disable_timing sb_0__0_/chanx_right_out[8] set_disable_timing sb_0__0_/chanx_right_in[8] +set_disable_timing sb_0__0_/chanx_right_out[9] set_disable_timing sb_0__0_/chanx_right_in[9] set_disable_timing sb_0__0_/chanx_right_out[10] set_disable_timing sb_0__0_/chanx_right_in[10] +set_disable_timing sb_0__0_/chanx_right_out[11] set_disable_timing sb_0__0_/chanx_right_in[11] set_disable_timing sb_0__0_/chanx_right_out[12] set_disable_timing sb_0__0_/chanx_right_in[12] @@ -757,7 +775,9 @@ set_disable_timing sb_0__0_/mux_right_track_10/in[0] set_disable_timing sb_0__0_/mux_right_track_12/in[0] set_disable_timing sb_0__0_/mux_right_track_14/in[0] set_disable_timing sb_0__0_/mux_right_track_16/in[0] +set_disable_timing sb_0__0_/mux_right_track_18/in[0] set_disable_timing sb_0__0_/mux_right_track_20/in[0] +set_disable_timing sb_0__0_/mux_right_track_22/in[0] set_disable_timing sb_0__0_/mux_right_track_24/in[0] set_disable_timing sb_0__0_/mux_right_track_0/in[0] set_disable_timing sb_0__0_/mux_top_track_24/in[2] @@ -782,6 +802,7 @@ set_disable_timing sb_0__1_/chanx_right_out[1] set_disable_timing sb_0__1_/chanx_right_out[2] set_disable_timing sb_0__1_/chanx_right_in[2] set_disable_timing sb_0__1_/chanx_right_out[3] +set_disable_timing sb_0__1_/chanx_right_in[3] set_disable_timing sb_0__1_/chanx_right_out[4] set_disable_timing sb_0__1_/chanx_right_in[4] set_disable_timing sb_0__1_/chanx_right_out[5] @@ -817,9 +838,11 @@ set_disable_timing sb_0__1_/chany_bottom_out[6] set_disable_timing sb_0__1_/chany_bottom_in[7] set_disable_timing sb_0__1_/chany_bottom_out[7] set_disable_timing sb_0__1_/chany_bottom_in[8] +set_disable_timing sb_0__1_/chany_bottom_out[8] set_disable_timing sb_0__1_/chany_bottom_in[9] set_disable_timing sb_0__1_/chany_bottom_out[9] set_disable_timing sb_0__1_/chany_bottom_in[10] +set_disable_timing sb_0__1_/chany_bottom_out[10] set_disable_timing sb_0__1_/chany_bottom_in[11] set_disable_timing sb_0__1_/chany_bottom_out[11] set_disable_timing sb_0__1_/chany_bottom_in[12] @@ -893,7 +916,9 @@ set_disable_timing sb_0__1_/mux_bottom_track_3/in[3] set_disable_timing sb_0__1_/mux_bottom_track_15/in[3] set_disable_timing sb_0__1_/mux_bottom_track_17/in[2] set_disable_timing sb_0__1_/mux_bottom_track_23/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_21/in[0] set_disable_timing sb_0__1_/mux_bottom_track_19/in[0] +set_disable_timing sb_0__1_/mux_bottom_track_17/in[0] set_disable_timing sb_0__1_/mux_bottom_track_15/in[0] set_disable_timing sb_0__1_/mux_bottom_track_13/in[0] set_disable_timing sb_0__1_/mux_bottom_track_11/in[0] @@ -922,9 +947,11 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2] set_disable_timing sb_1__0_/chany_top_in[0] set_disable_timing sb_1__0_/chany_top_out[1] set_disable_timing sb_1__0_/chany_top_in[1] +set_disable_timing sb_1__0_/chany_top_out[2] set_disable_timing sb_1__0_/chany_top_in[2] set_disable_timing sb_1__0_/chany_top_out[3] set_disable_timing sb_1__0_/chany_top_in[3] +set_disable_timing sb_1__0_/chany_top_out[4] set_disable_timing sb_1__0_/chany_top_in[4] set_disable_timing sb_1__0_/chany_top_out[5] set_disable_timing sb_1__0_/chany_top_in[5] @@ -958,9 +985,11 @@ set_disable_timing sb_1__0_/chanx_left_in[7] set_disable_timing sb_1__0_/chanx_left_out[7] set_disable_timing sb_1__0_/chanx_left_in[8] set_disable_timing sb_1__0_/chanx_left_out[8] +set_disable_timing sb_1__0_/chanx_left_in[9] set_disable_timing sb_1__0_/chanx_left_out[9] set_disable_timing sb_1__0_/chanx_left_in[10] set_disable_timing sb_1__0_/chanx_left_out[10] +set_disable_timing sb_1__0_/chanx_left_in[11] set_disable_timing sb_1__0_/chanx_left_out[11] set_disable_timing sb_1__0_/chanx_left_in[12] set_disable_timing sb_1__0_/chanx_left_out[12] @@ -1050,7 +1079,9 @@ set_disable_timing sb_1__0_/mux_top_track_16/in[2] set_disable_timing sb_1__0_/mux_top_track_14/in[3] set_disable_timing sb_1__0_/mux_top_track_12/in[2] set_disable_timing sb_1__0_/mux_top_track_10/in[2] +set_disable_timing sb_1__0_/mux_top_track_8/in[2] set_disable_timing sb_1__0_/mux_top_track_6/in[2] +set_disable_timing sb_1__0_/mux_top_track_4/in[2] set_disable_timing sb_1__0_/mux_top_track_2/in[3] ################################################## # Disable timing for Switch block sb_1__1_ @@ -1058,9 +1089,11 @@ set_disable_timing sb_1__0_/mux_top_track_2/in[3] set_disable_timing sb_1__1_/chany_bottom_out[0] set_disable_timing sb_1__1_/chany_bottom_in[1] set_disable_timing sb_1__1_/chany_bottom_out[1] +set_disable_timing sb_1__1_/chany_bottom_in[2] set_disable_timing sb_1__1_/chany_bottom_out[2] set_disable_timing sb_1__1_/chany_bottom_in[3] set_disable_timing sb_1__1_/chany_bottom_out[3] +set_disable_timing sb_1__1_/chany_bottom_in[4] set_disable_timing sb_1__1_/chany_bottom_out[4] set_disable_timing sb_1__1_/chany_bottom_in[5] set_disable_timing sb_1__1_/chany_bottom_out[5] @@ -1082,6 +1115,7 @@ set_disable_timing sb_1__1_/chanx_left_in[1] set_disable_timing sb_1__1_/chanx_left_in[2] set_disable_timing sb_1__1_/chanx_left_out[2] set_disable_timing sb_1__1_/chanx_left_in[3] +set_disable_timing sb_1__1_/chanx_left_out[3] set_disable_timing sb_1__1_/chanx_left_in[4] set_disable_timing sb_1__1_/chanx_left_out[4] set_disable_timing sb_1__1_/chanx_left_in[5] @@ -1166,6 +1200,7 @@ set_disable_timing sb_1__1_/mux_left_track_13/in[3] set_disable_timing sb_1__1_/mux_left_track_15/in[2] set_disable_timing sb_1__1_/mux_left_track_17/in[2] set_disable_timing sb_1__1_/mux_left_track_5/in[0] +set_disable_timing sb_1__1_/mux_left_track_7/in[0] set_disable_timing sb_1__1_/mux_left_track_9/in[0] set_disable_timing sb_1__1_/mux_left_track_11/in[0] set_disable_timing sb_1__1_/mux_left_track_13/in[0] @@ -1431,16 +1466,20 @@ set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/* ####################################### set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused grid[1][2][1] +# Disable Timing for unused resources in grid[1][2][1] ####################################### ####################################### -# Disable all the ports for pb_graph_node io[0] +# Disable unused pins for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/* +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/io_inpad[0] ####################################### -# Disable all the ports for pb_graph_node iopad[0] +# Disable unused mux_inputs for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] ####################################### # Disable Timing for unused grid[1][2][2] ####################################### @@ -1559,20 +1598,16 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc ####################################### set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] ####################################### -# Disable Timing for unused resources in grid[2][1][4] +# Disable Timing for unused grid[2][1][4] ####################################### ####################################### -# Disable unused pins for pb_graph_node io[0] +# Disable all the ports for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0] +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/* ####################################### -# Disable unused mux_inputs for pb_graph_node io[0] +# Disable all the ports for pb_graph_node iopad[0] ####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0] -####################################### -# Disable unused pins for pb_graph_node iopad[0] -####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* ####################################### # Disable Timing for unused grid[2][1][5] ####################################### diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v index 0e26d2bc1..7fe4b4b38 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -45,12 +45,11 @@ wire [0:0] clk_fm; // ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[14] ----- assign gfpga_pad_GPIO_PAD_fm[14] = b[0]; -// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] ----- - assign c[0] = gfpga_pad_GPIO_PAD_fm[12]; +// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[1] ----- + assign c[0] = gfpga_pad_GPIO_PAD_fm[1]; // ----- Wire unused FPGA I/Os to constants ----- assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0; - assign gfpga_pad_GPIO_PAD_fm[1] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0; @@ -60,6 +59,7 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0; @@ -132,8 +132,8 @@ initial begin force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; + force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; @@ -154,8 +154,8 @@ initial begin force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; - force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; @@ -238,12 +238,12 @@ initial begin force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; @@ -288,12 +288,12 @@ initial begin force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; @@ -302,12 +302,12 @@ initial begin force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10; - force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10; - force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; @@ -382,8 +382,8 @@ initial begin force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; @@ -426,8 +426,8 @@ initial begin force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = 3'b001; + force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = 3'b110; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}}; @@ -474,8 +474,8 @@ initial begin force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101; - force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}}; diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit index f116aa10c..7c8512c57 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -155,31 +155,6 @@ 0 0 0 -1 -0 -1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 0 0 0 @@ -223,7 +198,32 @@ 0 0 1 -1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 0 0 1 @@ -301,12 +301,12 @@ 0 0 0 -1 -1 0 0 -1 -1 +0 +0 +0 +0 0 0 0 @@ -360,11 +360,6 @@ 1 1 1 -1 -1 -1 -1 -1 0 1 1 @@ -378,6 +373,11 @@ 1 1 1 +1 +1 +1 +1 +1 0 0 0 @@ -459,11 +459,11 @@ 0 0 0 -1 0 0 0 -1 +0 +0 0 0 0 @@ -472,12 +472,12 @@ 1 0 0 -1 -1 -0 -0 -1 -1 +0 +0 +0 +0 +0 +0 0 0 0 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml index 12a7a85bd..c42176d6b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -314,11 +314,11 @@ - + - + @@ -398,7 +398,7 @@ - + @@ -448,9 +448,9 @@ - + - + @@ -606,17 +606,17 @@ - + - + - + - + @@ -724,7 +724,7 @@ - + @@ -734,7 +734,7 @@ - + @@ -922,7 +922,7 @@ - + @@ -930,7 +930,7 @@ - + @@ -948,17 +948,17 @@ - + - + - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml index 283d346ab..1b1ecfa0d 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml @@ -553,7 +553,7 @@ - + @@ -731,7 +731,7 @@ - + @@ -1480,15 +1480,15 @@ - + - + - - - + + + @@ -1516,15 +1516,15 @@ - + - + - - - + + + @@ -1961,16 +1961,16 @@ - + - + - - - + + + @@ -2002,11 +2002,11 @@ - + - - - + + + @@ -2098,13 +2098,13 @@ - + - + - - + + @@ -2136,13 +2136,13 @@ - + - + - - + + @@ -2864,16 +2864,16 @@ - + - + - - - + + + @@ -2902,7 +2902,7 @@ - + @@ -3128,7 +3128,7 @@ - + @@ -3174,7 +3174,7 @@ - + @@ -3266,7 +3266,7 @@ - + @@ -3287,7 +3287,7 @@ - + @@ -3341,12 +3341,12 @@ - + - + - + @@ -3382,7 +3382,7 @@ - + @@ -3403,7 +3403,7 @@ - + @@ -3541,7 +3541,7 @@ - + @@ -3616,7 +3616,7 @@ - + @@ -3662,7 +3662,7 @@ - + @@ -3754,7 +3754,7 @@ - + @@ -3775,7 +3775,7 @@ - + @@ -3845,7 +3845,7 @@ - + @@ -3866,7 +3866,7 @@ - + @@ -3891,18 +3891,18 @@ - + - + - - + + - + @@ -3912,7 +3912,7 @@ - + @@ -4004,7 +4004,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc index c169fa409..f072bac09 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/global_ports.sdc @@ -14,7 +14,7 @@ set_units -time s ################################################## # Create clock ################################################## -create_clock -name clk[0] -period 1.618133072e-09 -waveform {0 8.09066536e-10} [get_ports {clk[0]}] +create_clock -name clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} [get_ports {clk[0]}] ################################################## # Create programmable clock ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml index 9e63dda8a..89523007a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/pin_mapping.xml @@ -5,5 +5,5 @@ - +