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[Arch] Update sample arch using local clock from physical tile ports

This commit is contained in:
tangxifan 2020-11-10 14:31:58 -07:00
parent 4ca2a129c2
commit d127304760
1 changed files with 2 additions and 2 deletions
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openfpga_flow/openfpga_arch/k4_N4_40nm_local_clock_cc_openfpga.xml
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@ -169,7 +169,7 @@
<segment name="L4" circuit_model_name="chan_segment"/> <segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment> </routing_segment>
<tile_annotation> <tile_annotation>
<global_port tile_port="clb.clk" circuit_port="DFFSRQ.clk"/> <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
</tile_annotation> </tile_annotation>
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->