From d0fe8d96faa67fbb810d81a6e621e23d2d7edee5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 14 Feb 2022 16:03:48 -0800 Subject: [PATCH] [Test] Update template scripts and assoicated test cases by offering more options --- .../full_testbench_example_without_ace_script.openfpga | 2 +- .../benchmark_sweep/counter8_full_testbench/config/task.conf | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga index 8aadce77b..948730335 100644 --- a/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} ${OPENFPGA_FULL_TESTBENCH_OPTIONS} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/task.conf index f8b1f1fe2..e9e119237 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter8_full_testbench/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_full_testbench_options= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml