From d0e05b3575736e58eee88d9ffad22c9d340a9b1e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Jan 2021 21:35:43 -0700 Subject: [PATCH] [Lib] Now use pb_type in design constraints instead of physical tiles --- .../repack_design_constraint_example.xml | 8 ++++---- .../src/read_xml_repack_design_constraints.cpp | 4 ++-- .../librepackdc/src/repack_design_constraints.cpp | 14 +++++++------- .../librepackdc/src/repack_design_constraints.h | 12 ++++++------ .../src/write_xml_repack_design_constraints.cpp | 2 +- .../config/repack_pin_constraints.xml | 8 ++++---- 6 files changed, 24 insertions(+), 24 deletions(-) diff --git a/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml b/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml index 4c0a8cdde..a2f270da8 100644 --- a/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml +++ b/libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml @@ -1,7 +1,7 @@ - - - - + + + + diff --git a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp index 315dac045..47f10a156 100644 --- a/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp @@ -38,8 +38,8 @@ void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint, "Fail to create design constraint!\n"); } - repack_design_constraints.set_tile(design_constraint_id, - get_attribute(xml_pin_constraint, "tile", loc_data).as_string()); + repack_design_constraints.set_pb_type(design_constraint_id, + get_attribute(xml_pin_constraint, "pb_type", loc_data).as_string()); openfpga::PortParser port_parser(get_attribute(xml_pin_constraint, "pin", loc_data).as_string()); diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.cpp b/libopenfpga/librepackdc/src/repack_design_constraints.cpp index 87e6aa48a..d19c1ba71 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/repack_design_constraints.cpp @@ -32,10 +32,10 @@ RepackDesignConstraints::e_design_constraint_type RepackDesignConstraints::type( return repack_design_constraint_types_[repack_design_constraint_id]; } -std::string RepackDesignConstraints::tile(const RepackDesignConstraintId& repack_design_constraint_id) const { +std::string RepackDesignConstraints::pb_type(const RepackDesignConstraintId& repack_design_constraint_id) const { /* validate the design_constraint_id */ VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); - return repack_design_constraint_tiles_[repack_design_constraint_id]; + return repack_design_constraint_pb_types_[repack_design_constraint_id]; } openfpga::BasicPort RepackDesignConstraints::pin(const RepackDesignConstraintId& repack_design_constraint_id) const { @@ -60,7 +60,7 @@ bool RepackDesignConstraints::empty() const { void RepackDesignConstraints::reserve_design_constraints(const size_t& num_design_constraints) { repack_design_constraint_ids_.reserve(num_design_constraints); repack_design_constraint_types_.reserve(num_design_constraints); - repack_design_constraint_tiles_.reserve(num_design_constraints); + repack_design_constraint_pb_types_.reserve(num_design_constraints); repack_design_constraint_pins_.reserve(num_design_constraints); repack_design_constraint_nets_.reserve(num_design_constraints); } @@ -71,18 +71,18 @@ RepackDesignConstraintId RepackDesignConstraints::create_design_constraint(const repack_design_constraint_ids_.push_back(repack_design_constraint_id); repack_design_constraint_types_.push_back(repack_design_constraint_type); - repack_design_constraint_tiles_.emplace_back(); + repack_design_constraint_pb_types_.emplace_back(); repack_design_constraint_pins_.emplace_back(); repack_design_constraint_nets_.emplace_back(); return repack_design_constraint_id; } -void RepackDesignConstraints::set_tile(const RepackDesignConstraintId& repack_design_constraint_id, - const std::string& tile) { +void RepackDesignConstraints::set_pb_type(const RepackDesignConstraintId& repack_design_constraint_id, + const std::string& pb_type) { /* validate the design_constraint_id */ VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); - repack_design_constraint_tiles_[repack_design_constraint_id] = tile; + repack_design_constraint_pb_types_[repack_design_constraint_id] = pb_type; } void RepackDesignConstraints::set_pin(const RepackDesignConstraintId& repack_design_constraint_id, diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.h b/libopenfpga/librepackdc/src/repack_design_constraints.h index c8b917edb..e770c5542 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.h +++ b/libopenfpga/librepackdc/src/repack_design_constraints.h @@ -49,8 +49,8 @@ class RepackDesignConstraints { /* Get the type of constraint */ e_design_constraint_type type(const RepackDesignConstraintId& repack_design_constraint_id) const; - /* Get the tile name to be constrained */ - std::string tile(const RepackDesignConstraintId& repack_design_constraint_id) const; + /* Get the pb_type name to be constrained */ + std::string pb_type(const RepackDesignConstraintId& repack_design_constraint_id) const; /* Get the pin to be constrained */ openfpga::BasicPort pin(const RepackDesignConstraintId& repack_design_constraint_id) const; @@ -69,9 +69,9 @@ class RepackDesignConstraints { /* Add a design constraint to storage */ RepackDesignConstraintId create_design_constraint(const e_design_constraint_type& repack_design_constraint_type); - /* Set the tile name to be constrained */ - void set_tile(const RepackDesignConstraintId& repack_design_constraint_id, - const std::string& tile); + /* Set the pb_type name to be constrained */ + void set_pb_type(const RepackDesignConstraintId& repack_design_constraint_id, + const std::string& pb_type); /* Set the pin to be constrained */ void set_pin(const RepackDesignConstraintId& repack_design_constraint_id, @@ -91,7 +91,7 @@ class RepackDesignConstraints { vtr::vector repack_design_constraint_types_; /* Tiles to constraint */ - vtr::vector repack_design_constraint_tiles_; + vtr::vector repack_design_constraint_pb_types_; /* Pins to constraint */ vtr::vector repack_design_constraint_pins_; diff --git a/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp index ba0a00eb3..ec8f662fb 100644 --- a/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp @@ -42,7 +42,7 @@ int write_xml_pin_constraint(std::fstream& fp, return 1; } - write_xml_attribute(fp, "tile", repack_design_constraints.tile(design_constraint).c_str()); + write_xml_attribute(fp, "pb_type", repack_design_constraints.pb_type(design_constraint).c_str()); write_xml_attribute(fp, "pin", generate_xml_port_name(repack_design_constraints.pin(design_constraint)).c_str()); write_xml_attribute(fp, "net", repack_design_constraints.net(design_constraint).c_str()); diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml index ed4a49775..b64eafee5 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml @@ -6,9 +6,9 @@ - the clk[2] port of all the clb tiles available in the FPGA fabric - the clk[3] port of all the clb tiles available in the FPGA fabric --> - - - - + + + +