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Pushing duplicate pin fix for direct list to master branch 

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Laboratory for Nano Integrated Systems (LNIS) 2020-01-15 09:29:51 -07:00 committed by GitHub
parent 44ba0d826f 9e911cd288
commit d0da5ade52
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3 changed files with 57 additions and 5 deletions
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10
openfpga_flow/scripts/run_fpga_flow.py
View File

@ -580,7 +580,15 @@ def collect_files_for_vpr():
def run_vpr():
ExecTime["VPRStart"] = time.time()
# Format the BLIF File
cmd = r"mv %s.blif %s.blif.bak && cat %s.blif.bak" % (
args.top_module,
args.top_module,
args.top_module)
cmd += r"| sed 's/$/./' | fold -s -w80 "
cmd += r"| sed 's/[^.]$/ \\/' | sed 's/[.]$/ /'"
cmd += " > %s.blif" % args.top_module
os.system(cmd)
if not args.fix_route_chan_width:
# Run Standard VPR Flow
min_channel_width = run_standard_vpr(

39
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp
View File

@ -80,9 +80,12 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
/* Reach here, it means this pin is on this side */
int class_id = grid_type_descriptor->pin_class[ipin];
e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type;
/* Generate the pin name */
if (RECEIVER == pin_class_type) {
/* For each RECEIVER PIN, we do not duplicate */
/* Generate the pin name
* For each RECEIVER PIN or DRIVER PIN for direct connection,
* we do not duplicate in these cases */
if ( (RECEIVER == pin_class_type)
/* Xifan: I assume that each direct connection pin must have Fc=0. */
|| ( (DRIVER == pin_class_type) && (0. == grid_type_descriptor->Fc[ipin]) ) ) {
vtr::Point<size_t> dummy_coordinate;
std::string port_name = generate_grid_port_name(dummy_coordinate, iheight, side, ipin, false);
BasicPort grid_port(port_name, 0, 0);
@ -155,6 +158,36 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
if (1 != grid_type_descriptor->pinloc[pin_height][side][grid_pin_index]) {
continue;
}
/* Pins for direct connection are NOT duplicated.
* Follow the traditional recipe when adding nets!
* Xifan: I assume that each direct connection pin must have Fc=0.
*/
if (0. == grid_type_descriptor->Fc[grid_pin_index]) {
/* Create a net to connect the grid pin to child module pin */
ModuleNetId net = module_manager.create_module_net(grid_module);
/* Find the port in grid_module */
vtr::Point<size_t> dummy_coordinate;
std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_height, side, grid_pin_index, false);
ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
/* Grid port always has only 1 pin, it is assumed when adding these ports to the module
* if you need a change, please also change the port adding codes
*/
size_t grid_module_pin_id = 0;
/* Find the port in child module */
std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port);
ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id));
size_t child_module_pin_id = pb_graph_pin->pin_number;
/* Add net sources and sinks:
* For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin
*/
module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id);
continue;
}
/* Reach here, it means this pin is on this side */
/* Create a net to connect the grid pin to child module pin */
ModuleNetId net = module_manager.create_module_net(grid_module);

13
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.cpp
View File

@ -215,7 +215,18 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()];
size_t src_grid_pin_index = rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num;
size_t src_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, src_grid_pin_index);
std::string src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, sb_side2postfix_map[side_manager.get_side()]);
/* Pins for direct connection are NOT duplicated.
* Follow the traditional recipe when adding nets!
* Xifan: I assume that each direct connection pin must have Fc=0.
* For other duplicated pins, we follow the new naming
*/
std::string src_grid_port_name;
if (0. == grids[grid_coordinate.x()][grid_coordinate.y()].type->Fc[src_grid_pin_index]) {
src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, false);
} else {
src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, sb_side2postfix_map[side_manager.get_side()]);
}
ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id));
BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id);