Merge pull request #347 from lnis-uofu/testbench_force

Use ``force`` in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL

openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp

@@ -204,7 +204,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
  * while uses 'force' syntax to impost the bitstream at mem_inv port
  *******************************************************************/
 static 
-void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
+void print_verilog_preconfig_top_module_force_bitstream(std::fstream &fp,
                                                         const ModuleManager &module_manager,
                                                         const ModuleId &top_module,
                                                         const BitstreamManager &bitstream_manager,
@@ -214,6 +214,8 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
 
   print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----"));
 
+  fp << "initial begin" << std::endl;
+
   for (const ConfigBlockId &config_block_id : bitstream_manager.blocks()) {
     /* We only cares blocks with configuration bits */
     if (0 == bitstream_manager.block_bits(config_block_id).size()) {
@@ -242,31 +244,9 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
     for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) {
       config_data_values.push_back(bitstream_manager.bit_value(config_bit));
     }
-    print_verilog_wire_constant_values(fp, config_data_port, config_data_values);
+    print_verilog_force_wire_constant_values(fp, config_data_port, config_data_values);
-  }
 
     if (true == output_datab_bits) {
-    fp << "initial begin" << std::endl;
-
-    for (const ConfigBlockId &config_block_id : bitstream_manager.blocks()) {
-      /* We only cares blocks with configuration bits */
-      if (0 == bitstream_manager.block_bits(config_block_id).size()) {
-        continue;
-      }
-      /* Build the hierarchical path of the configuration bit in modules */
-      std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id);
-      /* Drop the first block, which is the top module, it should be replaced by the instance name here */
-      /* Ensure that this is the module we want to drop! */
-      VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0])));
-      block_hierarchy.erase(block_hierarchy.begin());
-      /* Build the full hierarchy path */
-      std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME);
-      for (const ConfigBlockId &temp_block : block_hierarchy) {
-        bit_hierarchy_path += std::string(".");
-        bit_hierarchy_path += bitstream_manager.block_name(temp_block);
-      }
-      bit_hierarchy_path += std::string(".");
-
       /* Find the bit index in the parent block */
       BasicPort config_datab_port(bit_hierarchy_path + generate_configurable_memory_inverted_data_out_name(),
                                   bitstream_manager.block_bits(config_block_id).size());
@@ -277,9 +257,9 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp,
       }
       print_verilog_force_wire_constant_values(fp, config_datab_port, config_datab_values);
     }
+  }
 
   fp << "end" << std::endl;
-  }
 
   print_verilog_comment(fp, std::string("----- End assign bitstream to configuration memories -----"));
 }
@@ -382,7 +362,7 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
 
   /* Use assign syntax for Icarus simulator */
   if (EMBEDDED_BITSTREAM_HDL_IVERILOG == embedded_bitstream_hdl_type) {
-    print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module,
+    print_verilog_preconfig_top_module_force_bitstream(fp, module_manager, top_module,
                                                        bitstream_manager,
                                                        output_datab_bits);
   /* Use deposit syntax for other simulators */

openfpga_flow/openfpga_cell_library/verilog/dff.v

@@ -20,12 +20,7 @@ always @ (posedge CK) begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
 assign Q = q_reg;
-`else
-  assign Q = 1'bZ;
-`endif
 
 endmodule //End Of Module
 
@@ -46,14 +41,8 @@ always @ (posedge CK) begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
 assign Q = q_reg;
 assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -79,12 +68,7 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
 assign Q = q_reg;
-`else
-  assign Q = 1'bZ;
-`endif
 
 endmodule //End Of Module
 
@@ -111,14 +95,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
 assign Q = q_reg;
 assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -144,14 +122,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
 assign Q = q_reg;
 assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -178,14 +150,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
 assign Q = q_reg;
 assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -211,14 +177,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
 assign Q = q_reg;
 assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -249,14 +209,8 @@ end else begin
   q_reg <= D;
 end
 
-// Wire q_reg to Q
-`ifndef ENABLE_FORMAL_VERIFICATION
 assign Q = q_reg;
 assign QN = ~q_reg;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -349,14 +303,8 @@ end else begin
   q_reg <= D;
 end
 
-`ifndef ENABLE_FORMAL_VERIFICATION
-// Wire q_reg to Q
 assign Q = q_reg;
 assign QN = !Q;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module
 
@@ -462,13 +410,7 @@ end
 assign CFGQ = CFGE ? Q : 1'b0;
 assign CFGQN = CFGE ? QN : 1'b1;
 
-`ifndef ENABLE_FORMAL_VERIFICATION
-// Wire q_reg to Q
 assign Q = q_reg;
 assign QN = !Q;
-`else
-  assign Q = 1'bZ;
-  assign QN = !Q;
-`endif
 
 endmodule //End Of Module