diff --git a/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act
new file mode 100644
index 000000000..43f1f55f1
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act
@@ -0,0 +1,3 @@
+a 0.5 0.5
+b 0.5 0.5
+c 0.25 0.75
diff --git a/openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif
new file mode 100644
index 000000000..941e6b51f
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif
@@ -0,0 +1,8 @@
+.model or2
+.inputs a b
+.outputs c
+
+.names a b c
+00 0
+
+.end
diff --git a/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
new file mode 100644
index 000000000..0f8dc04d9
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
@@ -0,0 +1,18 @@
+/////////////////////////////////////////
+//  Functionality: 2-input OR 
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module or2(
+  a,
+  b,
+  c);
+
+input wire a;
+input wire b;
+output wire c;
+
+assign c = a | b;
+
+endmodule
diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
index 97630512b..4db289d23 100644
--- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
@@ -25,7 +25,7 @@ openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_b
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2