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added fpgatoolperf vexriscv src

This commit is contained in:
Andrew Pond 2021-09-28 13:32:41 -06:00
parent 6cb51d1e7d
commit cebcdba4d4
13 changed files with 6415 additions and 9 deletions
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5760
openfpga_flow/benchmarks/processor/vexriscv/VexRiscv.v Normal file
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64
openfpga_flow/benchmarks/processor/vexriscv/vexriscv-verilog_wrap.v Normal file
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@ -0,0 +1,64 @@
/*
* Copyright (C) 2020 The SymbiFlow Authors.
*
* Use of this source code is governed by a ISC-style
* license that can be found in the LICENSE file or at
* https://opensource.org/licenses/ISC
*
* SPDX-License-Identifier: ISC
*/
/*
* Generated by harness_gen.py
* From: VexRiscv.v
*/
module top(input wire clk, input wire stb, input wire di, output wire do);
localparam integer DIN_N = 134;
localparam integer DOUT_N = 148;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
VexRiscv dut(
.externalResetVector(din[31:0]),
.timerInterrupt(din[32]),
.externalInterruptArray(din[64:33]),
.iBusWishbone_CYC(dout[0]),
.iBusWishbone_STB(dout[1]),
.iBusWishbone_ACK(din[65]),
.iBusWishbone_WE(dout[2]),
.iBusWishbone_ADR(dout[32:3]),
.iBusWishbone_DAT_MISO(din[97:66]),
.iBusWishbone_DAT_MOSI(dout[64:33]),
.iBusWishbone_SEL(dout[68:65]),
.iBusWishbone_ERR(din[98]),
.iBusWishbone_BTE(dout[70:69]),
.iBusWishbone_CTI(dout[73:71]),
.dBusWishbone_CYC(dout[74]),
.dBusWishbone_STB(dout[75]),
.dBusWishbone_ACK(din[99]),
.dBusWishbone_WE(dout[76]),
.dBusWishbone_ADR(dout[106:77]),
.dBusWishbone_DAT_MISO(din[131:100]),
.dBusWishbone_DAT_MOSI(dout[138:107]),
.dBusWishbone_SEL(dout[142:139]),
.dBusWishbone_ERR(din[132]),
.dBusWishbone_BTE(dout[144:143]),
.dBusWishbone_CTI(dout[147:145]),
.clk(clk),
.reset(din[133])
);
endmodule

0
openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v → openfpga_flow/benchmarks/processor/vexriscv_large.v
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0
openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v → openfpga_flow/benchmarks/processor/vexriscv_linux.v
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0
openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v → openfpga_flow/benchmarks/processor/vexriscv_small.v
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23
openfpga_flow/misc/fpgaflow_default_tool_path.conf
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@ -18,21 +18,28 @@ valid_flows = vpr_blif,yosys_vpr
[DEFAULT_PARSE_RESULT_VPR]
# parser format <name of variable> = <regex string>, <lambda function/type>
# io_blocks = "Netlist io blocks: ([0-9]+)", str
clb_blocks = "Netlist clb blocks: ([0-9]+)", str
io_blocks = "Netlist io blocks: ([0-9]+)", str
lut3s = "lut3\s+: ([0-9]+)", str
lut4s = "lut4\s+: ([0-9]+)", str
lut5s = "lut5\s+: ([0-9]+)", str
lut6s = "lut6\s+: ([0-9]+)", str
total_luts = "lut\s+: ([0-9]+)", str
mult_blocks = "Netlist mult_36 blocks: ([0-9]+)", str
memory_blocks = "Netlist memory blocks: ([0-9]+)", str
grid_tiles = "FPGA sized to ([0-9]+)", str
critical_path = "Final critical path: ([0-9.]+)", str
channel_width = "Circuit successfully routed with a channel width factor of ([0-9]+)", str
logic_delay = "Total logic delay: ([0-9.]+)", str
total_net_delay = "total net delay: ([0-9.]+)", str
total_routing_area = "Total routing area: ([0-9.]+)", str
total_logic_block_area = "Total used logic block area: ([0-9]+)", str
total_wire_length = "Total wirelength: ([0-9]+)", str
packing_time = "Packing took ([0-9.]+) seconds", str
placement_time = "Placement took ([0-9.]+) seconds", str
routing_time = "Routing took ([0-9.]+) seconds", str
average_net_length = "average net length: ([0-9.]+)", str
critical_path = "Final critical path: ([0-9.]+) ([a-z])s", scientific
total_routing_time = "Routing took ([0-9.]+) seconds", float
[DEFAULT_PARSE_RESULT_POWER]
pb_type_power="PB Types\s+([0-9]+)", str

2
openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga
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@ -2,7 +2,7 @@
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
# This is due to the Fc_in of clock port is set to 0 for global wiring
# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --disp on
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

18
openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram.txt Normal file
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@ -0,0 +1,18 @@
bram $__MY_DPRAM_1024x8
init 0
abits 10
dbits 8
groups 2
ports 1 1
wrmode 1 0
enable 1 1
transp 0 0
clocks 1 1
clkpol 1 1
endbram
match $__MY_DPRAM_1024x8
min efficiency 0
make_transp
endmatch

21
openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram_map.v Normal file
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@ -0,0 +1,21 @@
module $__MY_DPRAM_1024x8 (
output [0:7] B1DATA,
input CLK1,
input [0:9] B1ADDR,
input [0:9] A1ADDR,
input [0:7] A1DATA,
input A1EN,
input B1EN );
generate
dpram_1024x8 #() _TECHMAP_REPLACE_ (
.clk (CLK1),
.wen (A1EN),
.waddr (A1ADDR),
.data_in (A1DATA),
.ren (B1EN),
.raddr (B1ADDR),
.data_out (B1DATA) );
endgenerate
endmodule

220
openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v Normal file
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@ -0,0 +1,220 @@
//-----------------------------
// Dual-port RAM 128x8 bit (1Kbit)
// Core logic
//-----------------------------
module dpram_128x8_core (
input wclk,
input wen,
input [0:6] waddr,
input [0:7] data_in,
input rclk,
input ren,
input [0:6] raddr,
output [0:7] data_out );
reg [0:7] ram[0:127];
reg [0:7] internal;
assign data_out = internal;
always @(posedge wclk) begin
if(wen) begin
ram[waddr] <= data_in;
end
end
always @(posedge rclk) begin
if(ren) begin
internal <= ram[raddr];
end
end
endmodule
//-----------------------------
// Dual-port RAM 128x8 bit (1Kbit) wrapper
// where the read clock and write clock
// are combined to a unified clock
//-----------------------------
module dpram_128x8 (
input clk,
input wen,
input ren,
input [0:6] waddr,
input [0:6] raddr,
input [0:7] data_in,
output [0:7] data_out );
dpram_128x8_core memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (data_in),
.rclk (clk),
.ren (ren),
.raddr (raddr),
.data_out (data_out) );
endmodule
//-----------------------------
// 18-bit multiplier
//-----------------------------
module mult_18(
input [0:17] A,
input [0:17] B,
output [0:35] Y
);
assign Y = A * B;
endmodule
//-----------------------------
// Native D-type flip-flop
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dff(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
Q <= D;
1'b1:
always @(negedge C)
Q <= D;
endcase
endmodule
//-----------------------------
// D-type flip-flop with active-high asynchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffr(
output reg Q,
input D,
input R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge R)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or posedge R)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// D-type flip-flop with active-high asynchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffs(
output reg Q,
input D,
input S,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge S)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or posedge S)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
//-----------------------------
// D-type flip-flop with active-low asynchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffrn(
output reg Q,
input D,
input RN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// D-type flip-flop with active-low asynchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffsn(
output reg Q,
input D,
input SN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge SN)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or negedge SN)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule

48
openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v Normal file
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@ -0,0 +1,48 @@
// Basic DFF
module \$_DFF_P_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
// Async active-high reset
module \$_DFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Async active-high set
module \$_DFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Async active-low reset
module \$_DFF_PN0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
endmodule
// Async active-low set
module \$_DFF_PN1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
endmodule

220
openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm_cell_sim.v Normal file
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@ -0,0 +1,220 @@
//-----------------------------
// Dual-port RAM 1024x8 bit (1Kbit)
// Core logic
//-----------------------------
module dpram_1024x8_core (
input wclk,
input wen,
input [0:9] waddr,
input [0:7] data_in,
input rclk,
input ren,
input [0:9] raddr,
output [0:7] data_out );
reg [0:7] ram[0:1023];
reg [0:7] internal;
assign data_out = internal;
always @(posedge wclk) begin
if(wen) begin
ram[waddr] <= data_in;
end
end
always @(posedge rclk) begin
if(ren) begin
internal <= ram[raddr];
end
end
endmodule
//-----------------------------
// Dual-port RAM 1024x8 bit (1Kbit) wrapper
// where the read clock and write clock
// are combined to a unified clock
//-----------------------------
module dpram_1024x8 (
input clk,
input wen,
input ren,
input [0:9] waddr,
input [0:9] raddr,
input [0:7] data_in,
output [0:7] data_out );
dpram_1024x8_core memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (data_in),
.rclk (clk),
.ren (ren),
.raddr (raddr),
.data_out (data_out) );
endmodule
//-----------------------------
// 18-bit multiplier
//-----------------------------
module mult_18(
input [0:17] A,
input [0:17] B,
output [0:35] Y
);
assign Y = A * B;
endmodule
//-----------------------------
// Native D-type flip-flop
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dff(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
Q <= D;
1'b1:
always @(negedge C)
Q <= D;
endcase
endmodule
//-----------------------------
// D-type flip-flop with active-high asynchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffr(
output reg Q,
input D,
input R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge R)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or posedge R)
if (R == 1'b1)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// D-type flip-flop with active-high asynchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffs(
output reg Q,
input D,
input S,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge S)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or posedge S)
if (S == 1'b1)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
//-----------------------------
// D-type flip-flop with active-low asynchronous reset
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffrn(
output reg Q,
input D,
input RN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
//-----------------------------
// D-type flip-flop with active-low asynchronous set
//-----------------------------
(* abc9_flop, lib_whitebox *)
module dffsn(
output reg Q,
input D,
input SN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge SN)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or negedge SN)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule

48
openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm_dff_map.v Normal file
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@ -0,0 +1,48 @@
// Basic DFF
module \$_DFF_P_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
// Async active-high reset
module \$_DFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Async active-high set
module \$_DFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Async active-low reset
module \$_DFF_PN0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
endmodule
// Async active-low set
module \$_DFF_PN1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
endmodule