From cea43c2c4529ba8b4fd8598228996085b2540451 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 16 Mar 2021 18:04:31 -0600
Subject: [PATCH] [HDL] Add SPRAM module to generic yosys tech lib for openfpga
 usage

---
 .../openfpga_adders_sim.v                     | 15 +++++++++
 .../openfpga_brams_sim.v                      | 31 ++++++++++++++-----
 2 files changed, 38 insertions(+), 8 deletions(-)
 create mode 100644 openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v

diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v
new file mode 100644
index 000000000..9d82dc715
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v
@@ -0,0 +1,15 @@
+//---------------------------------------
+// 1-bit adder 
+//---------------------------------------
+module adder(
+	input cin,
+	input a,
+	input b,
+	output cout,
+	output sumout );
+
+
+	assign sumout = a ^ b ^ cin;
+	assign cout = (a & b) | ((a | b) & cin);
+
+endmodule
diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
index 514aefd85..5f8a12e5a 100644
--- a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
+++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
@@ -48,15 +48,30 @@ module dual_port_sram (
 
 endmodule
 
-module adder(
-	input cin,
-	input a,
-	input b,
-	output cout,
-	output sumout );
+//---------------------------------------
+// A single-port 32x8bit RAM 
+// This module is tuned for VTR's benchmarks
+//---------------------------------------
+module single_port_ram (
+	input clk,
+	input we,
+	input [4:0] addr,
+	input [7:0] data,
+	output [7:0] out );
 
+	reg [7:0] ram[31:0];
+	reg [7:0] internal;
 
-	assign sumout = a ^ b ^ cin;
-	assign cout = (a & b) | ((a | b) & cin);
+	assign out = internal;
+
+	always @(posedge clk) begin
+		if(wen) begin
+			ram[addr] <= data;
+		end
+
+		if(ren) begin
+			internal <= ram[addr];
+		end
+	end
 
 endmodule