[Arch] Enriched DFF model to support active-low/high FFs
This commit is contained in:
tangxifan
parent
adfea88be2
commit
ce6018e123
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@ -139,15 +139,16 @@
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<circuit_model type="ff" name="MULTI_MODE_DFFSRQ" prefix="MULTI_MODE_DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="S" lib_name="SET" size="1"/>
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<port type="input" prefix="R" lib_name="RST" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="C" lib_name="CK" size="1"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="0"/>
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</circuit_model>
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<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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@ -240,6 +241,9 @@
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<global_port name="op_reset" is_reset="true" default_val="0">
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<tile name="clb" port="reset"/>
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</global_port>
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<global_port name="op_set" is_set="true" default_val="0">
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<tile name="clb" port="set"/>
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</global_port>
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</tile_annotations>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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@ -257,7 +261,7 @@
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</pb_type>
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
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<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
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<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="MULTI_MODE_DFFSRQ" mode_bits="00"/>
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<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
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<!-- Binding operating pb_type to physical pb_type -->
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<!-- Binding operating pb_types in mode 'n2_lut5' -->
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@ -266,11 +270,18 @@
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<port name="in" physical_mode_port="in[0:4]"/>
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<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut5].ble5.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff">
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<pb_type name="clb.fle[n2_lut5].ble5.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00">
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<port name="clk" physical_mode_port="C"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut5].ble5.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<pb_type name="clb.fle[n2_lut5].ble5.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<pb_type name="clb.fle[n2_lut5].ble5.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
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<pb_type name="clb.fle[n2_lut5].ble5.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
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<pb_type name="clb.fle[n2_lut5].ble5.ff[dffs].dffs" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
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<pb_type name="clb.fle[n2_lut5].ble5.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="10">
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<port name="RN" physical_mode_port="R"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut5].ble5.ff[dffsn].dffsn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="01">
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<port name="SN" physical_mode_port="S"/>
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</pb_type>
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<!-- Binding operating pb_types in mode 'arithmetic' -->
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<pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
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<!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
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@ -278,22 +289,36 @@
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<port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
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<pb_type name="clb.fle[arithmetic].arithmetic.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff">
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<pb_type name="clb.fle[arithmetic].arithmetic.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00">
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<port name="clk" physical_mode_port="C"/>
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</pb_type>
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<pb_type name="clb.fle[arithmetic].arithmetic.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<pb_type name="clb.fle[arithmetic].arithmetic.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<pb_type name="clb.fle[arithmetic].arithmetic.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
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<pb_type name="clb.fle[arithmetic].arithmetic.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
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<pb_type name="clb.fle[arithmetic].arithmetic.ff[dffs].dffs" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
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<pb_type name="clb.fle[arithmetic].arithmetic.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="10">
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<port name="RN" physical_mode_port="R"/>
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</pb_type>
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<pb_type name="clb.fle[arithmetic].arithmetic.ff[dffsn].dffsn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="01">
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<port name="SN" physical_mode_port="S"/>
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</pb_type>
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<!-- Binding operating pb_types in mode 'ble6' -->
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<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
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<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:5]"/>
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<port name="out" physical_mode_port="lut6_out"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut6].ble6.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
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<pb_type name="clb.fle[n1_lut6].ble6.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
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<port name="clk" physical_mode_port="C"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut6].ble6.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
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<pb_type name="clb.fle[n1_lut6].ble6.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
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<pb_type name="clb.fle[n1_lut6].ble6.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
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<pb_type name="clb.fle[n1_lut6].ble6.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
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<pb_type name="clb.fle[n1_lut6].ble6.ff[dffs].dffs" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
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<pb_type name="clb.fle[n1_lut6].ble6.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="10" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
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<port name="RN" physical_mode_port="R"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut6].ble6.ff[dffsn].dffsn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="01" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
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<port name="SN" physical_mode_port="S"/>
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</pb_type>
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<!-- End physical pb_type binding in complex block clb -->
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<!-- physical pb_type binding in complex block dsp -->
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@ -147,7 +147,7 @@
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<port name="Y"/>
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</output_ports>
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</model>
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<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
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<!-- A virtual model for flip-flops -->
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<model name="dff">
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<input_ports>
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<port name="D" clock="C"/>
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@ -157,7 +157,17 @@
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
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<model name="dffsr">
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<input_ports>
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<port name="D" clock="C"/>
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<port name="R" clock="C"/>
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<port name="S" clock="C"/>
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<port name="C" is_clock="1"/>
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</input_ports>
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<output_ports>
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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<model name="dffr">
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<input_ports>
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<port name="D" clock="C"/>
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@ -168,6 +178,36 @@
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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<model name="dffs">
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<input_ports>
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<port name="D" clock="C"/>
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<port name="S" clock="C"/>
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<port name="C" is_clock="1"/>
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</input_ports>
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<output_ports>
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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<model name="dffrn">
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<input_ports>
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<port name="D" clock="C"/>
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<port name="RN" clock="C"/>
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<port name="C" is_clock="1"/>
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</input_ports>
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<output_ports>
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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<model name="dffsn">
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<input_ports>
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<port name="D" clock="C"/>
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<port name="SN" clock="C"/>
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<port name="C" is_clock="1"/>
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</input_ports>
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<output_ports>
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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</models>
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<tiles>
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<tile name="io" capacity="8" area="0">
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@ -190,6 +230,7 @@
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</equivalent_sites>
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<input name="I" num_pins="40" equivalent="full"/>
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<input name="cin" num_pins="1"/>
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<input name="set" num_pins="1" is_non_clock_global="true"/>
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<input name="reset" num_pins="1" is_non_clock_global="true"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<output name="cout" num_pins="1"/>
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@ -198,12 +239,13 @@
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<fc_override port_name="cin" fc_type="frac" fc_val="0"/>
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<fc_override port_name="cout" fc_type="frac" fc_val="0"/>
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<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
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<fc_override port_name="set" fc_type="frac" fc_val="0"/>
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<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
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</fc>
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<!-- Highly recommand to customize pin location when direct connection is used!!! -->
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<!--pinlocations pattern="spread"/-->
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<pinlocations pattern="custom">
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<loc side="left">clb.clk clb.reset</loc>
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<loc side="left">clb.clk clb.reset clb.set</loc>
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<loc side="top">clb.cin</loc>
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<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
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<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
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@ -412,6 +454,7 @@
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<pb_type name="clb">
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<input name="I" num_pins="40" equivalent="full"/>
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<input name="cin" num_pins="1"/>
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<input name="set" num_pins="1" is_non_clock_global="true"/>
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<input name="reset" num_pins="1" is_non_clock_global="true"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<output name="cout" num_pins="1"/>
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@ -423,6 +466,7 @@
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<pb_type name="fle" num_pb="10">
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<input name="in" num_pins="6"/>
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<input name="cin" num_pins="1"/>
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<input name="set" num_pins="1"/>
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<input name="reset" num_pins="1"/>
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<output name="out" num_pins="2"/>
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<output name="cout" num_pins="1"/>
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@ -432,6 +476,7 @@
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<pb_type name="fabric" num_pb="1">
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<input name="in" num_pins="6"/>
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<input name="cin" num_pins="1"/>
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<input name="set" num_pins="1"/>
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<input name="reset" num_pins="1"/>
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<output name="out" num_pins="2"/>
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<output name="cout" num_pins="1"/>
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@ -456,13 +501,15 @@
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</interconnect>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".subckt dffr" num_pb="2">
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<pb_type name="ff" blif_model=".subckt dffsr" num_pb="2">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="R" num_pins="1"/>
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<input name="S" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="C"/>
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<T_setup value="66e-12" port="ff.R" clock="C"/>
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<T_setup value="66e-12" port="ff.S" clock="C"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
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</pb_type>
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<!-- Define adders -->
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@ -491,6 +538,7 @@
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<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
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<complete name="direct10" input="fabric.clk" output="ff[1:0].C"/>
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<complete name="direct11" input="fabric.reset" output="ff[1:0].R"/>
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<complete name="direct12" input="fabric.set" output="ff[1:0].S"/>
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<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
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@ -510,6 +558,7 @@
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<direct name="direct4" input="fabric.cout" output="fle.cout"/>
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<direct name="direct5" input="fle.clk" output="fabric.clk"/>
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<direct name="direct6" input="fle.reset" output="fabric.reset"/>
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<direct name="direct7" input="fle.set" output="fabric.set"/>
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</interconnect>
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</mode>
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<!-- Physical mode definition end (physical implementation of the fle) -->
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@ -517,6 +566,7 @@
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<mode name="n2_lut5">
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<pb_type name="ble5" num_pb="2">
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<input name="in" num_pins="5"/>
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<input name="set" num_pins="1"/>
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<input name="reset" num_pins="1"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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@ -545,6 +595,7 @@
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<pb_type name="ff" num_pb="1">
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<input name="D" num_pins="1"/>
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<input name="R" num_pins="1"/>
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<input name="S" num_pins="1"/>
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<output name="Q" num_pins="1"/>
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<clock name="C" num_pins="1"/>
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<mode name="latch">
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@ -592,6 +643,57 @@
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<direct name="direct4" input="dffr.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dffrn">
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<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="RN" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dffrn.D" clock="C"/>
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<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
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<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ff.D" output="dffrn.D"/>
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<direct name="direct2" input="ff.C" output="dffrn.C"/>
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<direct name="direct3" input="ff.R" output="dffrn.RN"/>
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<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
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</interconnect>
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</mode>
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<mode name="dffs">
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<pb_type name="dffs" blif_model=".subckt dffs" num_pb="1">
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<input name="D" num_pins="1" port_class="D"/>
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<input name="S" num_pins="1"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="C" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="dffs.D" clock="C"/>
|
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<T_setup value="66e-12" port="dffs.S" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffs.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffs.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffs.C"/>
|
||||
<direct name="direct3" input="ff.S" output="dffs.S"/>
|
||||
<direct name="direct4" input="dffs.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffsn">
|
||||
<pb_type name="dffsn" blif_model=".subckt dffsn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="SN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffsn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffsn.SN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffsn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffsn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffsn.C"/>
|
||||
<direct name="direct3" input="ff.S" output="dffsn.SN"/>
|
||||
<direct name="direct4" input="dffsn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble5.in" output="lut5.in"/>
|
||||
|
|
@ -600,6 +702,7 @@
|
|||
</direct>
|
||||
<direct name="direct3" input="ble5.clk" output="ff.C"/>
|
||||
<direct name="direct4" input="ble5.reset" output="ff.R"/>
|
||||
<direct name="direct5" input="ble5.set" output="ff.S"/>
|
||||
<mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
|
||||
<delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
|
||||
|
|
@ -612,6 +715,7 @@
|
|||
<complete name="direct3" input="fle.clk" output="ble5.clk"/>
|
||||
<direct name="direct4" input="ble5.out" output="fle.out"/>
|
||||
<complete name="direct5" input="fle.reset" output="ble5.reset"/>
|
||||
<complete name="direct6" input="fle.set" output="ble5.set"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- END fle mode of dual lut5 -->
|
||||
|
|
@ -620,6 +724,7 @@
|
|||
<pb_type name="arithmetic" num_pb="2">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<input name="set" num_pins="1"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
|
|
@ -660,6 +765,7 @@
|
|||
<pb_type name="ff" num_pb="1">
|
||||
<input name="D" num_pins="1"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<input name="S" num_pins="1"/>
|
||||
<output name="Q" num_pins="1"/>
|
||||
<clock name="C" num_pins="1"/>
|
||||
<mode name="latch">
|
||||
|
|
@ -707,9 +813,61 @@
|
|||
<direct name="direct4" input="dffr.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffrn">
|
||||
<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="RN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffrn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffrn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffrn.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffrn.RN"/>
|
||||
<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffs">
|
||||
<pb_type name="dffs" blif_model=".subckt dffs" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="S" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffs.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffs.S" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffs.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffs.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffs.C"/>
|
||||
<direct name="direct3" input="ff.S" output="dffs.S"/>
|
||||
<direct name="direct4" input="dffs.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffsn">
|
||||
<pb_type name="dffsn" blif_model=".subckt dffsn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="SN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffsn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffsn.SN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffsn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffsn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffsn.C"/>
|
||||
<direct name="direct3" input="ff.S" output="dffsn.SN"/>
|
||||
<direct name="direct4" input="dffsn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="clock" input="arithmetic.clk" output="ff.C"/>
|
||||
<direct name="set" input="arithmetic.set" output="ff.S"/>
|
||||
<direct name="reset" input="arithmetic.reset" output="ff.R"/>
|
||||
<direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
|
||||
<direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
|
||||
|
|
@ -746,13 +904,15 @@
|
|||
</direct>
|
||||
<complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
|
||||
<complete name="direct4" input="fle.reset" output="arithmetic.reset"/>
|
||||
<direct name="direct5" input="arithmetic.out" output="fle.out"/>
|
||||
<complete name="direct5" input="fle.set" output="arithmetic.set"/>
|
||||
<direct name="direct6" input="arithmetic.out" output="fle.out"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- n2_lut5 -->
|
||||
<mode name="n1_lut6">
|
||||
<pb_type name="ble6" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<input name="set" num_pins="1"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
|
|
@ -782,6 +942,7 @@
|
|||
<pb_type name="ff" num_pb="1">
|
||||
<input name="D" num_pins="1"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<input name="S" num_pins="1"/>
|
||||
<output name="Q" num_pins="1"/>
|
||||
<clock name="C" num_pins="1"/>
|
||||
<mode name="latch">
|
||||
|
|
@ -829,6 +990,57 @@
|
|||
<direct name="direct4" input="dffr.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffrn">
|
||||
<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="RN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffrn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffrn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffrn.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffrn.RN"/>
|
||||
<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffs">
|
||||
<pb_type name="dffs" blif_model=".subckt dffs" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="S" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffs.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffs.S" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffs.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffs.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffs.C"/>
|
||||
<direct name="direct3" input="ff.S" output="dffs.S"/>
|
||||
<direct name="direct4" input="dffs.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffsn">
|
||||
<pb_type name="dffsn" blif_model=".subckt dffsn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="SN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffsn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffsn.SN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffsn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffsn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffsn.C"/>
|
||||
<direct name="direct3" input="ff.S" output="dffsn.SN"/>
|
||||
<direct name="direct4" input="dffsn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
||||
|
|
@ -837,6 +1049,7 @@
|
|||
</direct>
|
||||
<direct name="direct3" input="ble6.clk" output="ff.C"/>
|
||||
<direct name="direct4" input="ble6.reset" output="ff.R"/>
|
||||
<direct name="direct5" input="ble6.set" output="ff.S"/>
|
||||
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
||||
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
|
||||
|
|
@ -848,6 +1061,7 @@
|
|||
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||||
<direct name="direct4" input="fle.reset" output="ble6.reset"/>
|
||||
<direct name="direct5" input="fle.set" output="ble6.set"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- n1_lut6 -->
|
||||
|
|
@ -871,6 +1085,8 @@
|
|||
</complete>
|
||||
<complete name="resets" input="clb.reset" output="fle[9:0].reset">
|
||||
</complete>
|
||||
<complete name="sets" input="clb.set" output="fle[9:0].set">
|
||||
</complete>
|
||||
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||||
|
|
|
|||
Loading…
Reference in New Issue