riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added explicit checking to VVP execution

This commit is contained in:
Ganesh Gore 2019-09-18 12:14:26 -06:00
parent 169732ccc1
commit cd5fd6ce6c
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
openfpga_flow/scripts/run_fpga_flow.py
View File

@ -854,12 +854,14 @@ def run_netlists_verification():
command += [tb_top_autochecked]
run_command("iverilog_verification", "iverilog_output.txt", command)
vvp_command = ["vvp", "-Nvs", compiled_file]
vvp_command = ["vvp", compiled_file]
output = run_command("vvp_verification", "vvp_sim_output.txt", vvp_command)
if "Succeed" in output:
logger.info("VVP Simulation Successful")
else:
logger.info(str(output).split("\n")[-1])
logger.error(str(output).split("\n")[-1])
if exit_if_fail:
clean_up_and_exit("Failed to run VVP verification")
ExecTime["VerificationEnd"] = time.time()