[Benchmark] Change multi-clock counter from 8-bit to 4-bit

openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act

@@ -0,0 +1,22 @@
+clk0 0.505000 0.204400
+rst0 0.491000 0.206000
+clk1 0.472000 0.204400
+rst1 0.501400 0.204600
+q1[0] 0.278800 0.557400
+q1[1] 0.240600 0.268800
+q1[2] 0.178200 0.120000
+q1[3] 0.098400 0.041600
+q0[0] 0.283400 0.566600
+q0[1] 0.246800 0.272000
+q0[2] 0.181000 0.122200
+q0[3] 0.093200 0.048800
+n34 0.178200 0.068356
+n38 0.098400 0.002698
+$abc$226$new_n22_ 0.880800 0.004943
+n42 0.283400 0.129291
+n46 0.246800 0.084119
+n50 0.181000 0.067113
+n54 0.093200 0.002644
+$abc$226$new_n27_ 0.883200 0.005398
+n26 0.278800 0.038636
+n30 0.240600 0.082416

openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif

@@ -0,0 +1,48 @@
+# Benchmark "counter4bit_2clock" written by ABC on Wed Jan 13 13:27:00 2021
+.model counter4bit_2clock
+.inputs clk0 rst0 clk1 rst1 
+.outputs q0[0] q0[1] q0[2] q0[3] q1[0] q1[1] \
+q1[2] q1[3] 
+
+.latch n26 q1[0] re clk1 2
+.latch n30 q1[1] re clk1 2
+.latch n34 q1[2] re clk1 2
+.latch n38 q1[3] re clk1 2
+.latch n42 q0[0] re clk0 2
+.latch n46 q0[1] re clk0 2
+.latch n50 q0[2] re clk0 2
+.latch n54 q0[3] re clk0 2
+
+.names q1[0] q1[1] rst1 q1[2] n34
+-001 1
+0-01 1
+1100 1
+.names rst1 $abc$226$new_n22_ n38
+00 1
+.names q1[2] q1[0] q1[1] q1[3] $abc$226$new_n22_
+--00 1
+-0-0 1
+0--0 1
+1111 1
+.names rst0 q0[0] n42
+00 1
+.names rst0 q0[1] q0[0] n46
+001 1
+010 1
+.names q0[1] q0[0] rst0 q0[2] n50
+-001 1
+0-01 1
+1100 1
+.names rst0 $abc$226$new_n27_ n54
+00 1
+.names q0[2] q0[1] q0[0] q0[3] $abc$226$new_n27_
+--00 1
+-0-0 1
+0--0 1
+1111 1
+.names q1[0] rst1 n26
+00 1
+.names rst1 q1[0] q1[1] n30
+001 1
+010 1
+.end

openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v

@@ -0,0 +1,29 @@
+module counter4bit_2clock(clk0, q0, rst0, clk1, q1, rst1);
+
+    input clk0;
+    input rst0;
+    output [3:0] q0;
+    reg [3:0] q0;
+
+    input clk1;
+    input rst1;
+    output [3:0] q1;
+    reg [3:0] q1;
+
+    always @ (posedge clk0)
+    begin
+        if(rst0)
+		q0 <= 4'b0000;
+	else
+		q0 <= q0 + 1;
+    end
+
+    always @ (posedge clk1)
+    begin
+        if(rst1)
+		q1 <= 4'b0000;
+	else
+		q1 <= q1 + 1;
+    end
+
+endmodule

openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v

@@ -0,0 +1,42 @@
+module counter4bit_2clock_tb;
+
+	reg clk0, rst0;
+	wire [3:0] q0;
+
+	reg clk1, rst1;
+	wire [3:0] q1;
+
+	counter_2clock C_1(
+		clk0, 
+		q0, 
+		rst0);
+
+	counter_2clock C_1(
+		clk1, 
+		q1, 
+		rst1);
+	
+	initial begin
+		#0 rst0 = 1'b1; clk0 = 1'b0;
+		#100 rst0 = 1'b0;
+	end
+
+	always begin
+		#10 clk0 = ~clk0;
+	end
+
+	initial begin
+		#0 rst1 = 1'b1; clk1 = 1'b0;
+		#100 rst1 = 1'b0;
+	end
+
+	always begin
+		#20 clk1 = ~clk1;
+	end
+
+	
+	initial begin
+		#5000 $stop;
+	end
+
+endmodule