[core] developing new command to write module naming rules

libs/libnamemanager/src/io/write_xml_module_name_map.cpp

@@ -5,6 +5,8 @@
 /* Headers from system goes first */
 #include <algorithm>
 #include <string>
+#include <chrono>
+#include <ctime>
 
 /* Headers from vtr util library */
 #include "vtr_assert.h"
@@ -23,6 +25,29 @@
 
 namespace openfpga {  // Begin namespace openfpga
 
+/********************************************************************
+ * This function write header information to a bitstream file
+ *******************************************************************/
+static void write_xml_module_name_map_file_head(std::fstream& fp,
+                                                const bool& include_time_stamp) {
+  valid_file_stream(fp);
+
+  fp << "<!--" << std::endl;
+  fp << "\t- Module Naming rules" << std::endl;
+  fp << "\t- Author: Xifan TANG" << std::endl;
+  fp << "\t- Organization: RapidFlex" << std::endl;
+
+  if (include_time_stamp) {
+    auto end = std::chrono::system_clock::now();
+    std::time_t end_time = std::chrono::system_clock::to_time_t(end);
+    fp << "\t- Date: " << std::ctime(&end_time);
+  }
+
+  fp << "-->" << std::endl;
+  fp << std::endl;
+}
+
+
 /********************************************************************
  * A writer to output a I/O name mapping to XML format
  *
@@ -64,7 +89,9 @@ static int write_xml_module_name_binding(std::fstream& fp,
  * Return 2 if fail when creating files
  *******************************************************************/
 int write_xml_module_name_map(const char* fname,
-                              const ModuleNameMap& module_name_map) {
+                              const ModuleNameMap& module_name_map,
+                              const bool& include_time_stamp,
+                              const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Write module renaming rules");
 
   /* Create a file handler */
@@ -75,6 +102,8 @@ int write_xml_module_name_map(const char* fname,
   /* Validate the file stream */
   openfpga::check_file_stream(fname, fp);
 
+  write_xml_module_name_map_file_head(fp, include_time_stamp);
+
   /* Write the root node */
   fp << "<" << XML_MODULE_NAMES_ROOT_NAME;
   fp << ">"
@@ -83,6 +112,7 @@ int write_xml_module_name_map(const char* fname,
   int err_code = 0;
 
   /* Write each port */
+  size_t cnt = 0;
   for (std::string built_in_name : module_name_map.tags()) {
     /* Write bus */
     err_code =
@@ -90,6 +120,7 @@ int write_xml_module_name_map(const char* fname,
     if (0 != err_code) {
       return err_code;
     }
+    cnt++;
   }
 
   /* Finish writing the root node */
@@ -99,6 +130,8 @@ int write_xml_module_name_map(const char* fname,
   /* Close the file stream */
   fp.close();
 
+  VTR_LOGV(verbose, "Outputted %lu naming rules.\n", cnt);
+
   return err_code;
 }
 

libs/libnamemanager/src/io/write_xml_module_name_map.h

@@ -14,7 +14,9 @@
 namespace openfpga {  // Begin namespace openfpga
 
 int write_xml_module_name_map(const char* fname,
-                              const ModuleNameMap& module_name_map);
+                              const ModuleNameMap& module_name_map,
+                              const bool& include_time_stamp,
+                              const bool& verbose);
 
 }  // End of namespace openfpga
 

libs/libnamemanager/test/xml_io_module_name_map.cpp

@@ -30,7 +30,7 @@ int main(int argc, const char** argv) {
    * This is optional only used when there is a second argument
    */
   if (3 <= argc) {
-    status = openfpga::write_xml_module_name_map(argv[2], module_name_map);
+    status = openfpga::write_xml_module_name_map(argv[2], module_name_map, true, true);
     VTR_LOG("Write the module name mapping to an XML file: %s.\n", argv[2]);
   }
 

openfpga/src/base/openfpga_build_fabric_template.h

@@ -19,6 +19,7 @@
 #include "read_xml_fabric_key.h"
 #include "read_xml_io_name_map.h"
 #include "read_xml_module_name_map.h"
+#include "write_xml_module_name_map.h"
 #include "read_xml_tile_config.h"
 #include "rename_modules.h"
 #include "vtr_log.h"
@@ -372,6 +373,32 @@ int rename_modules_template(T& openfpga_ctx, const Command& cmd,
                                cmd_context.option_enable(cmd, opt_verbose));
 }
 
+/********************************************************************
+ * Write module naming rules to a file
+ *******************************************************************/
+template <class T>
+int write_module_naming_rules_template(const T& openfpga_ctx, const Command& cmd,
+                            const CommandContext& cmd_context) {
+  CommandOptionId opt_verbose = cmd.option("verbose");
+  CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
+
+  /* Check the option '--file' is enabled or not
+   * Actually, it must be enabled as the shell interface will check
+   * before reaching this fuction
+   */
+  CommandOptionId opt_file = cmd.option("file");
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  std::string file_name = cmd_context.option_value(cmd, opt_file);
+
+  /* Write hierarchy to a file */
+  return write_xml_module_name_map(file_name.c_str(), openfpga_ctx.module_name_map(),
+                                   !cmd_context.option_enable(cmd, opt_no_time_stamp),
+                                   cmd_context.option_enable(cmd, opt_verbose));
+}
+
+
 } /* end namespace openfpga */
 
 #endif

openfpga/src/base/openfpga_setup_command_template.h

@@ -821,6 +821,41 @@ ShellCommandId add_rename_modules_command_template(
   return shell_cmd_id;
 }
 
+/********************************************************************
+ * - Add a command to Shell environment: write_module_naming_rules
+ * - Add associated options
+ * - Add command dependency
+ *******************************************************************/
+template <class T>
+ShellCommandId add_write_module_naming_rules_command_template(
+  openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
+  const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
+  Command shell_cmd("write_module_naming_rules");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_file = shell_cmd.add_option(
+    "file", true, "file path to the XML file that contains renaming rules");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add an option '--no_time_stamp' */
+  shell_cmd.add_option("no_time_stamp", false,
+                       "Do not print time stamp in output files");
+
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(
+    shell_cmd, "Output the naming rules for each module of an FPGA fabric to a given file", hidden);
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_const_execute_function(shell_cmd_id, write_module_naming_rules_template<T>);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+
 template <class T>
 void add_setup_command_templates(openfpga::Shell<T>& shell,
                                  const bool& hidden = false) {
@@ -1050,6 +1085,17 @@ void add_setup_command_templates(openfpga::Shell<T>& shell,
   cmd_dependency_rename_modules.push_back(build_fabric_cmd_id);
   add_rename_modules_command_template<T>(shell, openfpga_setup_cmd_class,
                                          cmd_dependency_rename_modules, hidden);
+
+  /********************************
+   * Command 'write_module_naming_rules'
+   */
+  /* The 'write_module_naming_rules' command should NOT be executed before
+   * 'build_fabric' */
+  std::vector<ShellCommandId> cmd_dependency_write_module_naming_rules;
+  cmd_dependency_write_module_naming_rules.push_back(build_fabric_cmd_id);
+  add_write_module_naming_rules_command_template<T>(shell, openfpga_setup_cmd_class,
+                                         cmd_dependency_write_module_naming_rules, hidden);
+
 }
 
 } /* end namespace openfpga */