deploy openfpga shell in Travis CI
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@ -18,6 +18,11 @@ end_section "OpenFPGA.build"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd -
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###############################################
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# OpenFPGA with VPR7
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# TO BE DEPRECATED
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##############################################
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echo -e "Testing single-mode architectures";
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python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
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#python3 openfpga_flow/scripts/run_fpga_task.py s298
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@ -37,4 +42,13 @@ python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_t
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echo -e "Testing Verilog generation with grid pin duplication ";
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python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show_thread_logs
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###############################################
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# OpenFPGA Shell with VPR8
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# (Will replace all the old tests)
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##############################################
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echo -e "Testing OpenFPGA Shell";
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echo -e "Testing Verilog generation with simple fracturable LUT6 ";
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python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs
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end_section "OpenFPGA.TaskTun"
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