[Test] Now travis and github actions share the common regression test scripts
This commit is contained in:
tangxifan
parent
ab3c41715e
commit
cba07b6020
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@ -5,108 +5,6 @@ set -e
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd ${TRAVIS_BUILD_DIR}
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cd ${TRAVIS_BUILD_DIR}
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###############################################
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source .github/workflows/basic_reg_test.sh
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# OpenFPGA Shell with VPR8
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##############################################
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echo -e "Basic regression tests";
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echo -e "Testing configuration chain of a K4N4 FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
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echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
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echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
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echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
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echo -e "Testing fixed device layout and routing channel width";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs
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echo -e "Testing fabric Verilog generation only";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs
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echo -e "Testing Verilog testbench generation only";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs
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echo -e "Testing separated Verilog fabric netlists and testbench locations";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
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echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs
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echo -e "Testing Secured FPGA fabrics";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
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echo -e "Testing K4 series FPGA";
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echo -e "Testing K4N4 with facturable LUTs";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
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echo -e "Testing K4N4 with hard adders";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
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echo -e "Testing K4N4 without local routing architecture";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
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echo -e "Testing K4N4 with block RAM";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
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echo -e "Testing K4N4 with multiple lengths of routing segments";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
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echo -e "Testing K4N4 with 32-bit fracturable multiplier";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
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echo -e "Testing K4N5 with pattern based local routing";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs
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echo -e "Testing different tile organizations";
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echo -e "Testing tiles with pins only on top and left sides";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs
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echo -e "Testing tiles with pins only on top and right sides";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs
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echo -e "Testing tiles with pins only on bottom and right sides";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs
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echo -e "Testing global port definition from tiles";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
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end_section "OpenFPGA.TaskTun"
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end_section "OpenFPGA.TaskTun"
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@ -5,22 +5,6 @@ set -e
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd ${TRAVIS_BUILD_DIR}
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cd ${TRAVIS_BUILD_DIR}
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###############################################
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source .github/workflows/fpga_bitstream_reg_test.sh
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# OpenFPGA Shell with VPR8
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##############################################
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echo -e "FPGA-Bitstream regression tests";
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echo -e "Testing bitstream generation for an auto-sized device";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
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echo -e "Testing bitstream generation for an 48x48 FPGA device";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs
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echo -e "Testing bitstream generation for an 96x96 FPGA device";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs
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echo -e "Testing loading architecture bitstream from an external file";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
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end_section "OpenFPGA.TaskTun"
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end_section "OpenFPGA.TaskTun"
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@ -5,12 +5,6 @@ set -e
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd ${TRAVIS_BUILD_DIR}
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cd ${TRAVIS_BUILD_DIR}
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###############################################
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source .github/workflows/fpga_sdc_reg_test.sh
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# OpenFPGA Shell with VPR8
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##############################################
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echo -e "FPGA-SDC regression tests";
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echo -e "Testing SDC generation with time units";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_sdc/sdc_time_unit --debug --show_thread_logs
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end_section "OpenFPGA.TaskTun"
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end_section "OpenFPGA.TaskTun"
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@ -5,12 +5,6 @@ set -e
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd ${TRAVIS_BUILD_DIR}
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cd ${TRAVIS_BUILD_DIR}
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###############################################
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source .github/workflows/fpga_spice_reg_test.sh
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# OpenFPGA Shell with VPR8
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##############################################
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echo -e "FPGA-SPICE regression tests";
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echo -e "Testing FPGA-SPICE with netlist generation";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs
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end_section "OpenFPGA.TaskTun"
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end_section "OpenFPGA.TaskTun"
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@ -5,116 +5,6 @@ set -e
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd ${TRAVIS_BUILD_DIR}
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cd ${TRAVIS_BUILD_DIR}
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###############################################
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source .github/workflows/fpga_verilog_reg_test.sh
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# OpenFPGA Shell with VPR8
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##############################################
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echo -e "FPGA-Verilog Feature Tests";
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echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs
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echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
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echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
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echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
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echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
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echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs
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echo -e "Testing Verilog generation with hard adder chain in CLBs ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs
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echo -e "Testing Verilog generation with 16k block RAMs ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs
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echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
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echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
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echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs
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echo -e "Testing Verilog generation with embedded I/Os for an FPGA ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/embedded_io --debug --show_thread_logs
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echo -e "Testing Verilog generation with SoC I/Os for an FPGA ";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/soc_io --debug --show_thread_logs
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echo -e "Testing Verilog generation with adder chain across an FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
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echo -e "Testing Verilog generation with shift register chain across an FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
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echo -e "Testing Verilog generation with scan chain across an FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers without buffers";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
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|
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echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
|
|
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
|
|
||||||
|
|
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echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
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|
||||||
|
|
||||||
echo -e "Testing Verilog generation with routing multiplexers with constant gnd input";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing Verilog generation with routing multiplexers without constant inputs";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing Verilog generation with behavioral description";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing implicit Verilog generation";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing Verilog generation with flatten routing modules";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing Verilog generation with duplicated grid output pins";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing Verilog generation with spy output pads";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
|
|
||||||
|
|
||||||
|
|
||||||
echo -e "Testing Power-gating designs";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
|
|
||||||
|
|
||||||
echo -e "Testing Depopulated crossbar in local routing";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing Fully connected output crossbar in local routing";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
|
|
||||||
|
|
||||||
echo -e "Testing through channels in tileable routing";
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
|
|
||||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
|
|
||||||
|
|
||||||
# Verify MCNC big20 benchmark suite with ModelSim
|
|
||||||
# Please make sure you have ModelSim installed in the environment
|
|
||||||
# Otherwise, it will fail
|
|
||||||
#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
|
|
||||||
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
|
|
||||||
|
|
||||||
end_section "OpenFPGA.TaskTun"
|
end_section "OpenFPGA.TaskTun"
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue