From cb74d120e775807a02ccfcbebc0c422a6c613a47 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 17:31:05 -0600 Subject: [PATCH] shadow ini writer to help debugging --- vpr7_x2p/vpr/CMakeLists.txt | 8 ++--- .../verilog/simulation_info_writer.cpp | 11 +++++-- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 6 +++- .../verilog/verilog_formality_autodeck.c | 32 +++++++++---------- 4 files changed, 33 insertions(+), 24 deletions(-) diff --git a/vpr7_x2p/vpr/CMakeLists.txt b/vpr7_x2p/vpr/CMakeLists.txt index 0fa11717e..81751b3d6 100644 --- a/vpr7_x2p/vpr/CMakeLists.txt +++ b/vpr7_x2p/vpr/CMakeLists.txt @@ -65,14 +65,14 @@ if (ENABLE_VPR_GRAPHIC_CXX_FLAG) libarchfpga X11 libvtrutil - readline - libini) + #libini + readline) else () target_link_libraries(libvpr libarchfpga libvtrutil - readline - libini) + #libini + readline) endif() #Create the executables diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp index 11ab48b74..f486ecf05 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp @@ -5,8 +5,8 @@ #include #include #include -#define MINI_CASE_SENSITIVE -#include "ini.h" +//#define MINI_CASE_SENSITIVE +//#include "ini.h" /* Include vpr structs*/ #include "util.h" @@ -30,7 +30,9 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, const int& num_operating_clock_cycles, const float& prog_clock_freq, const float& op_clock_freq) { + /* mINI::INIStructure ini; + */ // std::map units_map; // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; // units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15; @@ -41,7 +43,7 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, 1. / prog_clock_freq, num_operating_clock_cycles, 1. / op_clock_freq); - + /* ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject"; ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name; ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string("_top_formal_verification_random_tb"); @@ -50,6 +52,7 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir); ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(defines_verilog_file_name); ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + "_include_netlists.v"); + */ /* Use default name if user does not provide one */ std::string ini_fname; @@ -59,6 +62,8 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, ini_fname = simulation_ini_filename; } + /* mINI::INIFile file(ini_fname); file.generate(ini, true); + */ } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index c80264bf0..8991680a8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -418,11 +418,13 @@ void vpr_fpga_verilog(ModuleManager& module_manager, std::string(src_dir_path)); /* Output script for formality */ + /* write_formality_script(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, fm_dir_path, src_dir_path, chomped_circuit_name, *(Arch.spice)); + */ /* Print out top-level testbench using random vectors */ std::string random_top_testbench_file_path = std::string(src_dir_path) @@ -432,9 +434,10 @@ void vpr_fpga_verilog(ModuleManager& module_manager, std::string(src_dir_path), L_logical_blocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); } - + if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) { /* Print exchangeable files which contains simulation settings */ + /* print_verilog_simulation_info(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path), std::string(format_dir_path(chomped_parent_dir)), std::string(chomped_circuit_name), @@ -443,6 +446,7 @@ void vpr_fpga_verilog(ModuleManager& module_manager, Arch.spice->spice_params.meas_params.sim_num_clock_cycle, Arch.spice->spice_params.stimulate_params.prog_clock_freq, Arch.spice->spice_params.stimulate_params.op_clock_freq); + */ } if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c index 33f587a75..1ffa58bea 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c @@ -10,8 +10,8 @@ #include #include #include -#define MINI_CASE_SENSITIVE -#include "ini.h" +//#define MINI_CASE_SENSITIVE +//#include "ini.h" /* Include vpr structs*/ #include "util.h" @@ -41,7 +41,7 @@ #include "verilog_routing.h" #include "verilog_tcl_utils.h" -mINI::INIStructure ini; +//mINI::INIStructure ini; static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chomped_circuit_name, char* inst_name){ int i, j; @@ -80,7 +80,7 @@ static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chompe inst_name, gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node)); sprintf(INI_lbl, "%s_reg", pb->name); - ini["REGISTER_MATCH"][INI_lbl] = WriteBuffer; + //ini["REGISTER_MATCH"][INI_lbl] = WriteBuffer; } //free(tmp); //Looks like is the cause of a double free, once free executated next iteration as no value in tmp return; @@ -199,11 +199,11 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, /* Load Verilog benchmark as reference */ fprintf(fp, "read_verilog -container r -libname WORK -05 { %s }\n", benchmark_path); - ini["BENCHMARK_INFO"]["benchmark_netlist "] = benchmark_path; + //ini["BENCHMARK_INFO"]["benchmark_netlist "] = benchmark_path; /* Set reference top */ fprintf(fp, "set_top r:/WORK/%s\n", chomped_circuit_name); - ini["BENCHMARK_INFO"]["src_top_module "] = chomped_circuit_name; + //ini["BENCHMARK_INFO"]["src_top_module "] = chomped_circuit_name; /* Load generated verilog as implemnetation */ fprintf(fp, "read_verilog -container i -libname WORK -05 { "); @@ -213,7 +213,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, sprintf(WriteBuffer, "%s%s%s", src_dir_formatted, chomped_circuit_name, verilog_top_postfix); sprintf(INI_lbl, "impl_netlist_%02d",FileCounter++); - ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; fprintf(fp, "%s%s%s ", src_dir_formatted, chomped_circuit_name, @@ -221,7 +221,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, sprintf(WriteBuffer, "%s%s%s\n", src_dir_formatted, chomped_circuit_name, formal_verification_verilog_file_postfix); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; init_include_user_defined_verilog_netlists(spice); // formality_include_user_defined_verilog_netlists(fp, spice); @@ -232,7 +232,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, assert(NULL != spice.include_netlists[i].path); fprintf(fp, "%s ", spice.include_netlists[i].path); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - ini["FPGA_INFO"][INI_lbl] = spice.include_netlists[i].path; + //ini["FPGA_INFO"][INI_lbl] = spice.include_netlists[i].path; spice.include_netlists[i].included = 1; } else { assert(1 == spice.include_netlists[i].included); @@ -246,7 +246,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, default_rr_dir_name, routing_verilog_file_name); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fprintf(fp, "%s%s%s ", src_dir_formatted, default_lb_dir_name, @@ -255,7 +255,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, default_lb_dir_name, logic_block_verilog_file_name); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fprintf(fp, "%s%s%s ", src_dir_formatted, default_submodule_dir_name, @@ -264,7 +264,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, default_submodule_dir_name, submodule_verilog_file_name); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; fprintf(fp, "}\n"); /* Set implementation top */ @@ -272,7 +272,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, formal_verification_top_postfix)); sprintf(WriteBuffer, "%s", my_strcat(chomped_circuit_name, formal_verification_top_postfix)); - ini["FPGA_INFO"]["impl_top_module"] = WriteBuffer; + //ini["FPGA_INFO"]["impl_top_module"] = WriteBuffer; /* Run matching */ fprintf(fp, "match\n"); @@ -299,7 +299,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix)); sprintf(INI_lbl, "%s", original_output_name); - ini["PORT_MATCHING"][INI_lbl] = WriteBuffer; + //ini["PORT_MATCHING"][INI_lbl] = WriteBuffer; } } } @@ -309,7 +309,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, /* Script END */ fclose(fp); - mINI::INIFile file(my_strcat(formality_script_file_name,".ini")); - file.generate(ini, true); + //mINI::INIFile file(my_strcat(formality_script_file_name,".ini")); + //file.generate(ini, true); return; }