[Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements

libopenfpga/libarchopenfpga/src/check_circuit_library.cpp

@@ -290,17 +290,33 @@ size_t check_ccff_circuit_model_ports(const CircuitLibrary& circuit_lib,
   VTR_ASSERT(CIRCUIT_MODEL_CCFF == circuit_lib.model_type(circuit_model));
 
   /* Check if we have D, Set and Reset */
+  /* We can have either 1 input which is D or 2 inputs which are D and scan input */
+  size_t num_input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true).size();
+  if ((1 != num_input_ports) && (2 != num_input_ports)) {
+    VTR_LOG_ERROR("Configuration flip-flop '%s' must have either 1 or 2 %s ports!\n\tAmong which the first input is a regular input (e.g., D) and the other could be scan-chain input (e.g., SI)\n",
+                  circuit_lib.model_name(circuit_model).c_str(),
+                  CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(CIRCUIT_MODEL_PORT_INPUT)]);
+    num_err++;
+  }
+
   num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, 
                                                                  CIRCUIT_MODEL_PORT_INPUT,
-                                                                 1, 1, false);
+                                                                 num_input_ports, 1, false);
   /* Check if we have a clock */
   num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, 
                                                                  CIRCUIT_MODEL_PORT_CLOCK,
                                                                  1, 1, true);
 
 
-  /* Check if we have 1 or 2 outputs */
+  /* Check if we have 2 or 4 outputs */
   size_t num_output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true).size();
+  if ((2 != num_output_ports) && (4 != num_output_ports)) {
+    VTR_LOG_ERROR("Configuration flip-flop '%s' must have either 2 or 4 %s ports!\n\tAmong which two manadatory outputs are regular data outputs (e.g., Q and QN) and the other two could be configure-enable outputs (e.g., cfg_en_Q and cgf_en_QN)\n",
+                  circuit_lib.model_name(circuit_model).c_str(),
+                  CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(CIRCUIT_MODEL_PORT_OUTPUT)]);
+    num_err++;
+  }
+
   num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, 
                                                                  CIRCUIT_MODEL_PORT_OUTPUT,
                                                                  num_output_ports, 1, false);