From cb09896f23b059a5f617fd689607d210d7eb0449 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 10 Jun 2020 15:41:46 -0600
Subject: [PATCH] add example simulation setting for openfpga flow

---
 .../auto_sim_openfpga.xml                     | 39 +++++++++++++++++++
 .../fixed_sim_openfpga.xml                    | 37 ++++++++++++++++++
 2 files changed, 76 insertions(+)
 create mode 100644 openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml

diff --git a/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml b/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
new file mode 100644
index 000000000..99ff97235
--- /dev/null
+++ b/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
@@ -0,0 +1,39 @@
+<!-- Simulation Setting for OpenFPGA framework
+     This file will use automatic inference for any settings
+     including:
+     - auto select the number of simulation cycles
+     - auto select the simulation clock frequency from VPR results
+  -->
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <programming frequency="100e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml b/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
new file mode 100644
index 000000000..94593863d
--- /dev/null
+++ b/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
@@ -0,0 +1,37 @@
+<!-- Simulation Setting for OpenFPGA framework
+     This file will use 
+     - a fixed simulation clock frequency
+  -->
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="500e6" num_cycles="10" slack="0.2"/>
+    <programming frequency="300e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>