From cab649893bdc8e10d21410ad612eb24b5a170452 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 26 Jun 2024 18:06:39 -0700
Subject: [PATCH] [core] update clock architecture

---
 libs/libclkarchopenfpga/arch/example.xml                 | 8 ++++----
 .../libclkarchopenfpga/arch/example_internal_drivers.xml | 9 +++++----
 .../config/clk_arch_1clk_1rst_2layer.xml                 | 4 ++--
 .../config/clk_arch_1clk_1rst_2layer_int_driver.xml      | 4 ++--
 .../homo_1clock_2layer/config/clk_arch_1clk_2layer.xml   | 2 +-
 .../config/clk_arch_1clk_2layer.xml                      | 2 +-
 .../homo_2clock_2layer/config/clk_arch_2clk_2layer.xml   | 4 ++--
 7 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/libs/libclkarchopenfpga/arch/example.xml b/libs/libclkarchopenfpga/arch/example.xml
index ac251bd3c..9cb31bdc6 100644
--- a/libs/libclkarchopenfpga/arch/example.xml
+++ b/libs/libclkarchopenfpga/arch/example.xml
@@ -17,10 +17,10 @@
     <spine name="rib_lvl1_lower_left" start_x="2" start_y="1" end_x="1" end_y="1"/> 
     <spine name="rib_lvl1_lower_right" start_x="2" start_y="1" end_x="3" end_y="1"/> 
     <taps>
-      <tap tile_pin="io[0:23].clk[0:7]"/>
-      <tap tile_pin="clb[0:0].clk[0:7]"/>
-      <tap tile_pin="dsp[0:0].clk[0:7]"/>
-      <tap tile_pin="bram[0:0].clk[0:7]"/>
+      <all from_pin="clk[0:0]" to_pin="io[0:23].clk[0:7]"/>
+      <all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:7]"/>
+      <all from_pin="clk[0:0]" to_pin="dsp[0:0].clk[0:7]"/>
+      <all from_pin="clk[0:0]" to_pin="bram[0:0].clk[0:7]"/>
     </taps>
   </clock_network>  
 </clock_networks> 
diff --git a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml
index 2b8a5fe0d..7a46a2094 100644
--- a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml
+++ b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml
@@ -21,10 +21,11 @@
     <spine name="rib_lvl1_lower_left" start_x="2" start_y="1" end_x="1" end_y="1"/> 
     <spine name="rib_lvl1_lower_right" start_x="2" start_y="1" end_x="3" end_y="1"/> 
     <taps>
-      <tap tile_pin="io[0:23].clk[0:7]"/>
-      <tap tile_pin="clb[0:0].clk[0:7]"/>
-      <tap tile_pin="dsp[0:0].clk[0:7]"/>
-      <tap tile_pin="bram[0:0].clk[0:7]"/>
+      <all from_pin="clk[0:0]" to_pin="io[0:23].clk[0:0]"/>
+      <all from_pin="clk[0:0]" to_pin="clb[0:0].clk[1:1]"/>
+      <all from_pin="clk[0:0]" to_pin="dsp[0:0].clk[2:2]"/>
+      <single from_pin="clk[0:0]" to_pin="bram[0:0].clk[3:7]" x="1" y="1"/>
+      <region from_pin="clk[0:0]" to_pin="bram[0:0].clk[3:7]" start_x="1" end_x="10" repeat_x="2" start_y="8" end_y="20" repeat_y="8"/>
     </taps>
   </clock_network>  
 </clock_networks> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml
index fde2c515a..6c05921c7 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml
@@ -11,7 +11,7 @@
     <spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <tap tile_pin="clb[0:0].clk[0:0]"/>
+      <all from_pin="rst[0:0]" to_pin="clb[0:0].clk[0:0]"/>
     </taps>
   </clock_network>  
   <clock_network name="rst_tree_2lvl" width="1"> 
@@ -26,7 +26,7 @@
     <spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <tap tile_pin="clb[0:0].reset[0:0]"/>
+      <all from_pin="rst[0:0]" to_pin="clb[0:0].reset[0:0]"/>
     </taps>
   </clock_network>  
 </clock_networks> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml
index 78f156469..ed43a26b5 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml
@@ -19,7 +19,7 @@
     <spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <tap tile_pin="clb[0:0].clk[0:0]"/>
+      <all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
     </taps>
   </clock_network>  
   <clock_network name="rst_tree_2lvl" width="1"> 
@@ -34,7 +34,7 @@
     <spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <tap tile_pin="clb[0:0].reset[0:0]"/>
+      <all from_pin="rst[0:0]" to_pin="clb[0:0].reset[0:0]"/>
     </taps>
   </clock_network>  
 </clock_networks> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml
index 6aaf1b9b4..7a41f1216 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml
@@ -11,7 +11,7 @@
     <spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <tap tile_pin="clb[0:0].clk[0:0]"/>
+      <all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
     </taps>
   </clock_network>  
 </clock_networks> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml
index 6aaf1b9b4..7a41f1216 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml
@@ -11,7 +11,7 @@
     <spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <tap tile_pin="clb[0:0].clk[0:0]"/>
+      <all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
     </taps>
   </clock_network>  
 </clock_networks> 
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
index fdf1dc149..8c224318c 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
@@ -11,8 +11,8 @@
     <spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
     <spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
     <taps>
-      <tap tile_pin="clb[0:0].clk[0:0]"/>
-      <tap tile_pin="clb[0:0].clk[1:1]"/>
+      <all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
+      <all from_pin="clk[1:1]" to_pin="clb[0:0].clk[1:1]"/>
     </taps>
   </clock_network>  
 </clock_networks>