diff --git a/.travis/script.sh b/.travis/script.sh index b577ee48c..231437e28 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -51,6 +51,9 @@ echo -e "Testing OpenFPGA Shell"; echo -e "Testing configuration chain of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs +echo -e "Testing Verilog generation for a single mode LUT6 FPGA using micro benchmarks"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/single_mode --debug --show_thread_logs + echo -e "Testing Verilog generation with simple fracturable LUT6 "; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs @@ -99,4 +102,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/flatten_routing -- echo -e "Testing Verilog generation with duplicated grid output pins"; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/duplicated_grid_pin --debug --show_thread_logs +echo -e "Testing Verilog generation with spy output pads"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/spypad --debug --show_thread_logs + end_section "OpenFPGA.TaskTun" diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst index 3712cea0d..543b87397 100644 --- a/docs/source/openfpga_shell/openfpga_commands.rst +++ b/docs/source/openfpga_shell/openfpga_commands.rst @@ -124,7 +124,9 @@ FPGA-Bitstream .. option:: build_fabric_bitstream - Reorganize the bitstream database for a specific FPGA fabric + Build a sequence for every configuration bits in the bitstream database for a specific FPGA fabric + + - ``--file`` or ``-f`` Output the fabric bitstream to an plain text file (only 0 or 1) - ``--verbose`` Show verbose log diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index cf8b8714f..a235e53af 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -777,7 +777,7 @@ std::vector CircuitLibrary::model_ports_by_type(const CircuitMode if ( type != port_type(port_id) ) { continue; } - /* We skip global ports if specified */ + /* We skip global ports if specified. Note: I/O port should be kept */ if ( (true == ignore_global_port) && (true == port_is_global(port_id)) ) { continue; diff --git a/openfpga/src/annotation/vpr_routing_annotation.cpp b/openfpga/src/annotation/vpr_routing_annotation.cpp index 1c17450ed..b51f4be94 100644 --- a/openfpga/src/annotation/vpr_routing_annotation.cpp +++ b/openfpga/src/annotation/vpr_routing_annotation.cpp @@ -36,9 +36,10 @@ void VprRoutingAnnotation::set_rr_node_net(const RRNodeId& rr_node, /* Ensure that the node_id is in the list */ VTR_ASSERT(size_t(rr_node) < rr_node_nets_.size()); /* Warn any override attempt */ - if (ClusterNetId::INVALID() != rr_node_nets_[rr_node]) { - VTR_LOG_WARN("Override the net '%ld' for node '%ld' with in routing context annotation!\n", - size_t(net_id), size_t(rr_node)); + if ( (ClusterNetId::INVALID() != rr_node_nets_[rr_node]) + && (net_id != rr_node_nets_[rr_node])) { + VTR_LOG_WARN("Override the net '%ld' by net '%ld' for node '%ld' with in routing context annotation!\n", + size_t(rr_node_nets_[rr_node]), size_t(net_id), size_t(rr_node)); } rr_node_nets_[rr_node] = net_id; diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp index 7e2a19fc4..e131a2bfc 100644 --- a/openfpga/src/base/openfpga_bitstream.cpp +++ b/openfpga/src/base/openfpga_bitstream.cpp @@ -12,7 +12,8 @@ #include "openfpga_digest.h" #include "build_device_bitstream.h" -#include "bitstream_writer.h" +#include "arch_bitstream_writer.h" +#include "fabric_bitstream_writer.h" #include "build_fabric_bitstream.h" #include "openfpga_bitstream.h" @@ -56,10 +57,24 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_file = cmd.option("file"); + /* Build fabric bitstream here */ openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(), openfpga_ctx.module_graph(), cmd_context.option_enable(cmd, opt_verbose)); + + /* Write fabric bitstream if required */ + if (true == cmd_context.option_enable(cmd, opt_file)) { + std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file)); + + /* Create directories */ + create_directory(src_dir_path); + + write_fabric_bitstream_to_text_file(openfpga_ctx.bitstream_manager(), + openfpga_ctx.fabric_bitstream(), + cmd_context.option_value(cmd, opt_file)); + } /* TODO: should identify the error code from internal function execution */ return CMD_EXEC_SUCCESS; diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp index b64696d79..70149dd43 100644 --- a/openfpga/src/base/openfpga_bitstream_command.cpp +++ b/openfpga/src/base/openfpga_bitstream_command.cpp @@ -76,6 +76,11 @@ ShellCommandId add_openfpga_fabric_bitstream_command(openfpga::Shell& dependent_cmds) { Command shell_cmd("build_fabric_bitstream"); + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option("file", false, "file path to output the fabric bitstream to plain text file"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Enable verbose output"); diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index 99d59afdb..0796d4df1 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -1325,14 +1325,28 @@ bool is_core_grid_on_given_border_side(const vtr::Point& device_size, * The name convention is * _ ********************************************************************/ -std::string generate_pb_type_port_name(t_port* pb_type_port) { +std::string generate_pb_type_port_name(t_pb_type* pb_type, + t_port* pb_type_port) { std::string port_name; - port_name = std::string(pb_type_port->parent_pb_type->name) + std::string("_") + std::string(pb_type_port->name); + port_name = std::string(pb_type->name) + std::string("_") + std::string(pb_type_port->name); return port_name; } +/********************************************************************* + * Generate the port name of a Verilog module describing a pb_type + * The name convention is + * _ + * + * This is a wrapper on the generate_pb_type_port_name() function + * which can infer the parent_pb_type + ********************************************************************/ +std::string generate_pb_type_port_name(t_port* pb_type_port) { + return generate_pb_type_port_name(pb_type_port->parent_pb_type, pb_type_port); +} + + /********************************************************************* * Generate the global I/O port name of a Verilog module * This is mainly used by I/O circuit models diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h index 40d7f05e9..d3307fe3c 100644 --- a/openfpga/src/base/openfpga_naming.h +++ b/openfpga/src/base/openfpga_naming.h @@ -238,6 +238,9 @@ bool is_core_grid_on_given_border_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate, const e_side& border_side); +std::string generate_pb_type_port_name(t_pb_type* pb_type, + t_port* pb_type_port); + std::string generate_pb_type_port_name(t_port* pb_type_port); std::string generate_fpga_global_io_port_name(const std::string& prefix, diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp index fe0529d04..a0fd143f4 100644 --- a/openfpga/src/base/openfpga_repack.cpp +++ b/openfpga/src/base/openfpga_repack.cpp @@ -37,7 +37,8 @@ int repack(OpenfpgaContext& openfpga_ctx, g_vpr_ctx.atom(), g_vpr_ctx.clustering(), openfpga_ctx.vpr_device_annotation(), - openfpga_ctx.arch().circuit_lib); + openfpga_ctx.arch().circuit_lib, + cmd_context.option_enable(cmd, opt_verbose)); /* TODO: should identify the error code from internal function execution */ return CMD_EXEC_SUCCESS; diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index 0d88bdc81..12090d43d 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -163,16 +163,36 @@ void add_primitive_module_fpga_global_io_port(ModuleManager& module_manager, BasicPort logic_io_port = module_manager.module_port(logic_module, logic_io_port_id); VTR_ASSERT(logic_io_port.get_width() == module_port.get_width()); - /* Wire the GPIO port form primitive_module to the logic module!*/ + /* Wire the GPIO port from primitive_module to the logic module!*/ for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(primitive_module); if ( (ModuleManager::MODULE_GPIO_PORT == module_io_port_type) || (ModuleManager::MODULE_GPIN_PORT == module_io_port_type) ) { - module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]); + bool net_exist = true; + /* If the source port has already a net to drive, we just update the net sinks */ + ModuleNetId net = module_manager.module_instance_port_net(primitive_module, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]); + if (net == ModuleNetId::INVALID()) { + net_exist = false; + net = module_manager.create_module_net(primitive_module); + } + + if (false == net_exist) { + module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]); + } module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]); } else { + bool net_exist = true; + /* If the source port has already a net to drive, we just update the net sinks */ + ModuleNetId net = module_manager.module_instance_port_net(primitive_module, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]); + if (net == ModuleNetId::INVALID()) { + net_exist = false; + net = module_manager.create_module_net(primitive_module); + } + VTR_ASSERT(ModuleManager::MODULE_GPOUT_PORT == module_io_port_type); - module_manager.add_module_net_source(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]); + + if (false == net_exist) { + module_manager.add_module_net_source(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]); + } module_manager.add_module_net_sink(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]); } } diff --git a/openfpga/src/fabric/build_lut_modules.cpp b/openfpga/src/fabric/build_lut_modules.cpp index 184de6698..2ba688e4d 100644 --- a/openfpga/src/fabric/build_lut_modules.cpp +++ b/openfpga/src/fabric/build_lut_modules.cpp @@ -45,7 +45,7 @@ void build_lut_module(ModuleManager& module_manager, /* Get the input ports from the mux */ std::vector lut_input_ports = circuit_lib.model_ports_by_type(lut_model, CIRCUIT_MODEL_PORT_INPUT, true); /* Get the output ports from the mux */ - std::vector lut_output_ports = circuit_lib.model_ports_by_type(lut_model, CIRCUIT_MODEL_PORT_OUTPUT, true); + std::vector lut_output_ports = circuit_lib.model_ports_by_type(lut_model, CIRCUIT_MODEL_PORT_OUTPUT, false); /* Classify SRAM ports into two categories: regular (not for mode select) and mode-select */ std::vector lut_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, lut_model); diff --git a/openfpga/src/fabric/build_mux_modules.cpp b/openfpga/src/fabric/build_mux_modules.cpp index 41cb68118..a28eac264 100644 --- a/openfpga/src/fabric/build_mux_modules.cpp +++ b/openfpga/src/fabric/build_mux_modules.cpp @@ -849,7 +849,7 @@ vtr::vector build_mux_module_output_buffers(ModuleMana vtr::vector mux_output_nets(mux_graph.num_outputs(), ModuleNetId::INVALID()); /* Get the output ports from the mux */ - std::vector mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, true); + std::vector mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, false); /* Iterate over all the outputs in the MUX module */ for (const auto& output_port : mux_output_ports) { @@ -1098,7 +1098,7 @@ void build_cmos_mux_module(ModuleManager& module_manager, /* Get the input ports from the mux */ std::vector mux_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true); /* Get the output ports from the mux */ - std::vector mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, true); + std::vector mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, false); /* Get the sram ports from the mux * Multiplexing structure does not mode_sram_ports, they are handled in LUT modules * Here we just bypass it. diff --git a/openfpga/src/fpga_bitstream/bitstream_writer.cpp b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp similarity index 99% rename from openfpga/src/fpga_bitstream/bitstream_writer.cpp rename to openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp index 6f8539d3f..6a87a6768 100644 --- a/openfpga/src/fpga_bitstream/bitstream_writer.cpp +++ b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp @@ -17,7 +17,7 @@ #include "openfpga_naming.h" #include "bitstream_manager_utils.h" -#include "bitstream_writer.h" +#include "arch_bitstream_writer.h" /* begin namespace openfpga */ namespace openfpga { diff --git a/openfpga/src/fpga_bitstream/bitstream_writer.h b/openfpga/src/fpga_bitstream/arch_bitstream_writer.h similarity index 91% rename from openfpga/src/fpga_bitstream/bitstream_writer.h rename to openfpga/src/fpga_bitstream/arch_bitstream_writer.h index 338bfde35..a66880735 100644 --- a/openfpga/src/fpga_bitstream/bitstream_writer.h +++ b/openfpga/src/fpga_bitstream/arch_bitstream_writer.h @@ -1,5 +1,5 @@ -#ifndef BITSTREAM_WRITER_H -#define BITSTREAM_WRITER_H +#ifndef ARCH_BITSTREAM_WRITER_H +#define ARCH_BITSTREAM_WRITER_H /******************************************************************** * Include header files that are required by function declaration diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp new file mode 100644 index 000000000..069a99345 --- /dev/null +++ b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp @@ -0,0 +1,61 @@ +/******************************************************************** + * This file includes functions that output a fabric-dependent + * bitstream database to files in different formats + *******************************************************************/ +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from openfpgautil library */ +#include "openfpga_digest.h" + +#include "openfpga_naming.h" + +#include "bitstream_manager_utils.h" +#include "fabric_bitstream_writer.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Write the fabric bitstream to a plain text file + * Notes: + * - This is the final bitstream which is loadable to the FPGA fabric + * (Verilog netlists etc.) + * - Do NOT include any comments or other characters that the 0|1 bitstream content + * in this file + *******************************************************************/ +void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream, + const std::string& fname) { + /* Ensure that we have a valid file name */ + if (true == fname.empty()) { + VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n"); + } + + std::string timer_message = std::string("Write ") + std::to_string(fabric_bitstream.size()) + std::string(" fabric bitstream into plain text file '") + fname + std::string("'"); + vtr::ScopedStartFinishTimer timer(timer_message); + + /* Create the file stream */ + std::fstream fp; + fp.open(fname, std::fstream::out | std::fstream::trunc); + + check_file_stream(fname.c_str(), fp); + + /* Put down pure 0|1 bitstream here */ + for (const ConfigBitId& fabric_bit : fabric_bitstream) { + fp << bitstream_manager.bit_value(fabric_bit); + } + /* Print an end to the file here */ + fp << std::endl; + + /* Close file handler */ + fp.close(); +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h new file mode 100644 index 000000000..6b2c0e771 --- /dev/null +++ b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h @@ -0,0 +1,24 @@ +#ifndef FABRIC_BITSTREAM_WRITER_H +#define FABRIC_BITSTREAM_WRITER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include +#include "bitstream_manager.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream, + const std::string& fname); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp index c6b50d797..4f748f9ad 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp @@ -281,6 +281,135 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir, fp.close(); } +/******************************************************************** + * Print SDC timing constraints for a primitive pb_type + * This function will generate SDC to constrain pin-to-pin timing + * if it is defined in XML + * + * This is designed for LUT, adder or other hard IPs + * When PnR the modules, we want to minimize the interconnect delay + *******************************************************************/ +static +void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir, + const ModuleManager& module_manager, + t_pb_graph_node* primitive_pb_graph_node, + const bool& constrain_zero_delay_paths) { + /* Validate pb_graph node */ + if (nullptr == primitive_pb_graph_node) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid primitive_pb_graph_node.\n"); + exit(1); + } + + t_pb_graph_node* logical_primitive_pb_graph_node = primitive_pb_graph_node; + + /* Get the pb_type where the timing annotations are stored + * Note that some primitive pb_type has child modes + * - Look-Up Table + * - Memory + * For those pb_type, timing annotations are stored in the child pb_type + */ + t_pb_type* primitive_pb_type = primitive_pb_graph_node->pb_type; + if (LUT_CLASS == primitive_pb_type->class_type) { + VTR_ASSERT(VPR_PB_TYPE_LUT_MODE < primitive_pb_type->num_modes); + VTR_ASSERT(1 == primitive_pb_type->modes[VPR_PB_TYPE_LUT_MODE].num_pb_type_children); + primitive_pb_type = &(primitive_pb_type->modes[VPR_PB_TYPE_LUT_MODE].pb_type_children[0]); + logical_primitive_pb_graph_node = primitive_pb_graph_node->child_pb_graph_nodes[VPR_PB_TYPE_LUT_MODE][0]; + VTR_ASSERT(nullptr != logical_primitive_pb_graph_node); + } else if (MEMORY_CLASS == primitive_pb_type->class_type) { + VTR_ASSERT(1 == primitive_pb_type->num_modes); + VTR_ASSERT(1 == primitive_pb_type->modes[0].num_pb_type_children); + primitive_pb_type = &(primitive_pb_type->modes[0].pb_type_children[0]); + logical_primitive_pb_graph_node = primitive_pb_graph_node->child_pb_graph_nodes[0][0]; + } + VTR_ASSERT(nullptr != primitive_pb_type); + VTR_ASSERT(nullptr != logical_primitive_pb_graph_node); + + /* We can directly return if there is no timing annotation defined */ + if (0 == primitive_pb_type->num_annotations) { + return; + } + + /* Get the pb_type definition related to the node */ + t_pb_type* physical_pb_type = primitive_pb_graph_node->pb_type; + std::string pb_module_name = generate_physical_block_module_name(physical_pb_type); + + /* Find the pb module in module manager */ + ModuleId pb_module = module_manager.find_module(pb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); + + /* Create the file name for SDC */ + std::string sdc_fname(sdc_dir + pb_module_name + std::string(SDC_FILE_NAME_POSTFIX)); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + check_file_stream(sdc_fname.c_str(), fp); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Timing constraints for Grid " + pb_module_name + " in PnR")); + + /* We traverse the pb_graph pins where we can find pin-to-pin timing annotation + * We walk through output pins here, build timing constraints by pair each output to input + * Clock pins are not walked through because they will be handled by clock tree synthesis + */ + for (int iport = 0; iport < logical_primitive_pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < logical_primitive_pb_graph_node->num_output_pins[iport]; ++ipin) { + t_pb_graph_pin* sink_pin = &(logical_primitive_pb_graph_node->output_pins[iport][ipin]); + + /* Port must exist in the module graph */ + ModulePortId sink_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, sink_pin->port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, sink_module_port_id)); + BasicPort sink_port = module_manager.module_port(pb_module, sink_module_port_id); + /* Set the correct pin number of the port */ + sink_port.set_width(sink_pin->pin_number, sink_pin->pin_number); + + /* Find all the sink pin from this source pb_graph_pin */ + for (int iedge = 0; iedge < sink_pin->num_input_edges; ++iedge) { + VTR_ASSERT(1 == sink_pin->input_edges[iedge]->num_input_pins); + t_pb_graph_pin* src_pin = sink_pin->input_edges[iedge]->input_pins[0]; + + /* Port must exist in the module graph */ + ModulePortId src_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, src_pin->port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, src_module_port_id)); + BasicPort src_port = module_manager.module_port(pb_module, src_module_port_id); + /* Set the correct pin number of the port */ + src_port.set_width(src_pin->pin_number, src_pin->pin_number); + + /* Find max delay between src and sink pin */ + float tmax = sink_pin->input_edges[iedge]->delay_max; + /* If the delay is zero, constrain only when user wants it */ + if ( (true == constrain_zero_delay_paths) + || (0. == tmax) ) { + print_pnr_sdc_constrain_max_delay(fp, + pb_module_name, + generate_sdc_port(src_port), + pb_module_name, + generate_sdc_port(sink_port), + tmax); + } + + /* Find min delay between src and sink pin */ + float tmin = sink_pin->input_edges[iedge]->delay_min; + /* If the delay is zero, constrain only when user wants it */ + if ( (true == constrain_zero_delay_paths) + || (0. == tmin) ) { + print_pnr_sdc_constrain_min_delay(fp, + pb_module_name, + generate_sdc_port(src_port), + pb_module_name, + generate_sdc_port(sink_port), + tmin); + } + } + } + } + + /* Close file handler */ + fp.close(); +} + /******************************************************************** * Recursively print SDC timing constraints for a pb_type * This function will generate a SDC file for each pb_type, @@ -302,8 +431,11 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir, /* Get the pb_type */ t_pb_type* parent_pb_type = parent_pb_graph_node->pb_type; - /* No need to constrain the primitive node */ + /* Constrain the primitive node if a timing matrix is defined */ if (true == is_primitive_pb_type(parent_pb_type)) { + print_pnr_sdc_constrain_primitive_pb_graph_node(sdc_dir, module_manager, + parent_pb_graph_node, + constrain_zero_delay_paths); return; } diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp index d4f1ce522..4bed8f16a 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp @@ -334,6 +334,52 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir, /* Generate the descriptions*/ print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR")); + /* Contrain each routing track inside the connection block */ + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + /* Create a port description for the input */ + std::string input_port_name = generate_cb_module_track_port_name(cb_type, + itrack, + IN_PORT); + ModulePortId input_port_id = module_manager.find_module_port(cb_module, input_port_name); + BasicPort input_port = module_manager.module_port(cb_module, input_port_id); + + /* Create a port description for the output */ + std::string output_port_name = generate_cb_module_track_port_name(cb_type, + itrack, + OUT_PORT); + ModulePortId output_port_id = module_manager.find_module_port(cb_module, output_port_name); + BasicPort output_port = module_manager.module_port(cb_module, output_port_id); + + /* Ensure port size matching */ + VTR_ASSERT(1 == input_port.get_width()); + VTR_ASSERT(input_port.get_width() == output_port.get_width()); + + /* Connection block routing segment ids for each track */ + RRSegmentId segment_id = rr_gsb.get_chan_node_segment(rr_gsb.get_cb_chan_side(cb_type), itrack); + + /* Computing the delay of the routing segment + * Here we just assume a simple 1-level RC delay model + * TODO: Should consider multi-level RC delay models + * where the number of levels are defined by users + */ + float routing_segment_delay = rr_graph.get_segment(segment_id).Rmetal + * rr_graph.get_segment(segment_id).Cmetal; + + /* If we have a zero-delay path to contrain, we will skip unless users want so */ + if ( (false == constrain_zero_delay_paths) + && (0. == routing_segment_delay) ) { + continue; + } + + /* Constrain a path with routing segment delay */ + print_pnr_sdc_constrain_port2port_timing(fp, + module_manager, + cb_module, input_port_id, + cb_module, output_port_id, + routing_segment_delay); + } + + /* Contrain each multiplexers inside the connection block */ std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); for (size_t side = 0; side < cb_sides.size(); ++side) { diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp index 328f87ce6..363d97e1c 100644 --- a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp +++ b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp @@ -87,6 +87,38 @@ void print_pnr_sdc_constrain_max_delay(std::fstream& fp, fp << std::endl; } +/******************************************************************** + * Constrain a path between two ports of a module with a given minimum timing value + *******************************************************************/ +void print_pnr_sdc_constrain_min_delay(std::fstream& fp, + const std::string& src_instance_name, + const std::string& src_port_name, + const std::string& des_instance_name, + const std::string& des_port_name, + const float& delay) { + /* Validate file stream */ + valid_file_stream(fp); + + fp << "set_min_delay"; + + fp << " -from "; + if (!src_instance_name.empty()) { + fp << src_instance_name << "/"; + } + fp << src_port_name; + + fp << " -to "; + + if (!des_instance_name.empty()) { + fp << des_instance_name << "/"; + } + fp << des_port_name; + + fp << " " << std::setprecision(10) << delay; + + fp << std::endl; +} + /******************************************************************** * Constrain a path between two ports of a module with a given timing value * Note: this function uses set_max_delay !!! diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.h b/openfpga/src/fpga_sdc/sdc_writer_utils.h index 4e0d86839..80f6e97e9 100644 --- a/openfpga/src/fpga_sdc/sdc_writer_utils.h +++ b/openfpga/src/fpga_sdc/sdc_writer_utils.h @@ -28,6 +28,13 @@ void print_pnr_sdc_constrain_max_delay(std::fstream& fp, const std::string& des_port_name, const float& delay); +void print_pnr_sdc_constrain_min_delay(std::fstream& fp, + const std::string& src_instance_name, + const std::string& src_port_name, + const std::string& des_instance_name, + const std::string& des_port_name, + const float& delay); + void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& input_parent_module_id, diff --git a/openfpga/src/fpga_verilog/simulation_info_writer.cpp b/openfpga/src/fpga_verilog/simulation_info_writer.cpp index fbbb7e83c..7c0bf0e3e 100644 --- a/openfpga/src/fpga_verilog/simulation_info_writer.cpp +++ b/openfpga/src/fpga_verilog/simulation_info_writer.cpp @@ -12,6 +12,9 @@ #include "vtr_assert.h" #include "vtr_time.h" +/* Headers from openfpgautil library */ +#include "openfpga_digest.h" + #include "simulation_utils.h" #include "verilog_constants.h" @@ -34,6 +37,11 @@ void print_verilog_simulation_info(const std::string& ini_fname, std::string timer_message = std::string("Write exchangeable file containing simulation information '") + ini_fname + std::string("'"); + std::string ini_dir_path = format_dir_path(find_path_dir_name(ini_fname)); + + /* Create directories */ + create_directory(ini_dir_path); + /* Start time count */ vtr::ScopedStartFinishTimer timer(timer_message); diff --git a/openfpga/src/mux_lib/mux_graph.cpp b/openfpga/src/mux_lib/mux_graph.cpp index 5b0f81828..d8066c055 100644 --- a/openfpga/src/mux_lib/mux_graph.cpp +++ b/openfpga/src/mux_lib/mux_graph.cpp @@ -1001,7 +1001,7 @@ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, void MuxGraph::add_fracturable_outputs(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { /* Iterate over output ports */ - for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true)) { + for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, false)) { /* Get the fracturable_level */ size_t frac_level = circuit_lib.port_lut_frac_level(port); /* Bypass invalid frac_level */ diff --git a/openfpga/src/repack/build_physical_truth_table.cpp b/openfpga/src/repack/build_physical_truth_table.cpp index 51fc93f93..404911a2d 100644 --- a/openfpga/src/repack/build_physical_truth_table.cpp +++ b/openfpga/src/repack/build_physical_truth_table.cpp @@ -11,15 +11,13 @@ #include "openfpga_naming.h" #include "lut_utils.h" +#include "pb_type_utils.h" #include "physical_pb.h" #include "build_physical_truth_table.h" /* begin namespace openfpga */ namespace openfpga { -/* Mode 1 is the lut mode while mode 0 is the wire mode */ -constexpr int VPR_PB_TYPE_LUT_MODE = 1; - /*************************************************************************************** * Identify if LUT is used as wiring * In this case, LUT functions as a buffer @@ -102,7 +100,8 @@ void build_physical_pb_lut_truth_tables(PhysicalPb& physical_pb, const PhysicalPbId& lut_pb_id, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, - const CircuitLibrary& circuit_lib) { + const CircuitLibrary& circuit_lib, + const bool& verbose) { const t_pb_graph_node* pb_graph_node = physical_pb.pb_graph_node(lut_pb_id); CircuitModelId lut_model = device_annotation.pb_type_circuit_model(physical_pb.pb_graph_node(lut_pb_id)->pb_type); @@ -125,20 +124,21 @@ void build_physical_pb_lut_truth_tables(PhysicalPb& physical_pb, continue; } /* Check if this is a LUT used as wiring */ - if (true == is_wired_lut(input_nets, output_net)) { - AtomNetlist::TruthTable wire_tt = build_wired_lut_truth_table(input_nets.size(), std::find(input_nets.begin(), input_nets.end(), output_net) - input_nets.begin()); - physical_pb.set_truth_table(lut_pb_id, output_pin, wire_tt); - continue; + AtomNetlist::TruthTable adapt_tt; + if (true == physical_pb.is_wire_lut_output(lut_pb_id, output_pin)) { + /* Double check: ensure that the output nets appear in the input net !!! */ + VTR_ASSERT(true == is_wired_lut(input_nets, output_net)); + adapt_tt = build_wired_lut_truth_table(input_nets.size(), std::find(input_nets.begin(), input_nets.end(), output_net) - input_nets.begin()); + } else { + /* Find the truth table from atom block which drives the atom net */ + const AtomBlockId& atom_blk = atom_ctx.nlist.net_driver_block(output_net); + VTR_ASSERT(true == atom_ctx.nlist.valid_block_id(atom_blk)); + const AtomNetlist::TruthTable& orig_tt = atom_ctx.nlist.block_truth_table(atom_blk); + + std::vector rotated_pin_map = generate_lut_rotated_input_pin_map(input_nets, atom_ctx, atom_blk, pb_graph_node); + adapt_tt = lut_truth_table_adaption(orig_tt, rotated_pin_map); } - /* Find the truth table from atom block which drives the atom net */ - const AtomBlockId& atom_blk = atom_ctx.nlist.net_driver_block(output_net); - VTR_ASSERT(true == atom_ctx.nlist.valid_block_id(atom_blk)); - const AtomNetlist::TruthTable& orig_tt = atom_ctx.nlist.block_truth_table(atom_blk); - - std::vector rotated_pin_map = generate_lut_rotated_input_pin_map(input_nets, atom_ctx, atom_blk, pb_graph_node); - const AtomNetlist::TruthTable& adapt_tt = lut_truth_table_adaption(orig_tt, rotated_pin_map); - /* Adapt the truth table for fracturable lut implementation and add to physical pb */ CircuitPortId lut_model_output_port = device_annotation.pb_circuit_port(output_pin->port); size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port); @@ -148,6 +148,29 @@ void build_physical_pb_lut_truth_tables(PhysicalPb& physical_pb, size_t lut_output_mask = circuit_lib.port_lut_output_mask(lut_model_output_port)[output_pin->pin_number]; const AtomNetlist::TruthTable& frac_lut_tt = adapt_truth_table_for_frac_lut(lut_frac_level, lut_output_mask, adapt_tt); physical_pb.set_truth_table(lut_pb_id, output_pin, frac_lut_tt); + + /* Print debug information */ + VTR_LOGV(verbose, "Input nets: "); + for (const AtomNetId& net : input_nets) { + if (AtomNetId::INVALID() == net) { + VTR_LOGV(verbose, "unconn "); + } else { + VTR_ASSERT(AtomNetId::INVALID() != net); + VTR_LOGV(verbose, "%s ", atom_ctx.nlist.net_name(net).c_str()); + } + } + VTR_LOGV(verbose, "\n"); + + VTR_ASSERT(AtomNetId::INVALID() != output_net); + VTR_LOGV(verbose, "Output net: %s\n", atom_ctx.nlist.net_name(output_net).c_str()); + + VTR_LOGV(verbose, + "Add following truth table to pb_graph_pin '%s[%d]'\n", + output_pin->port->name, output_pin->pin_number); + for (const std::string& tt_line : truth_table_to_string(frac_lut_tt)) { + VTR_LOGV(verbose, "\t%s\n", tt_line.c_str()); + } + VTR_LOGV(verbose, "\n"); } } } @@ -164,7 +187,8 @@ void build_physical_lut_truth_tables(VprClusteringAnnotation& cluster_annotation const AtomContext& atom_ctx, const ClusteringContext& cluster_ctx, const VprDeviceAnnotation& device_annotation, - const CircuitLibrary& circuit_lib) { + const CircuitLibrary& circuit_lib, + const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build truth tables for physical LUTs"); for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { @@ -178,7 +202,7 @@ void build_physical_lut_truth_tables(VprClusteringAnnotation& cluster_annotation } /* Reach here, we have a LUT to deal with. Find the truth tables that mapped to the LUT */ - build_physical_pb_lut_truth_tables(physical_pb, primitive_pb, atom_ctx, device_annotation, circuit_lib); + build_physical_pb_lut_truth_tables(physical_pb, primitive_pb, atom_ctx, device_annotation, circuit_lib, verbose); } } } diff --git a/openfpga/src/repack/build_physical_truth_table.h b/openfpga/src/repack/build_physical_truth_table.h index c5d14059f..3c0c8ebf3 100644 --- a/openfpga/src/repack/build_physical_truth_table.h +++ b/openfpga/src/repack/build_physical_truth_table.h @@ -20,7 +20,8 @@ void build_physical_lut_truth_tables(VprClusteringAnnotation& cluster_annotation const AtomContext& atom_ctx, const ClusteringContext& cluster_ctx, const VprDeviceAnnotation& device_annotation, - const CircuitLibrary& circuit_lib); + const CircuitLibrary& circuit_lib, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/repack/lb_router_utils.cpp b/openfpga/src/repack/lb_router_utils.cpp index 362ce4a76..1dea1750d 100644 --- a/openfpga/src/repack/lb_router_utils.cpp +++ b/openfpga/src/repack/lb_router_utils.cpp @@ -86,6 +86,16 @@ void save_lb_router_results_to_physical_pb(PhysicalPb& phy_pb, VTR_ASSERT(true == phy_pb.valid_pb_id(pb_id)); const AtomNetId& atom_net = lb_router.net_atom_net_id(net); + + /* Print info to help debug + bool verbose = true; + VTR_LOGV(verbose, + "\nSave net '%lu' to physical pb_graph_pin '%s.%s[%d]'\n", + size_t(atom_net), + pb_graph_pin->parent_node->pb_type->name, + pb_graph_pin->port->name, + pb_graph_pin->pin_number); + */ if (AtomNetId::INVALID() == phy_pb.pb_graph_pin_atom_net(pb_id, pb_graph_pin)) { phy_pb.set_pb_graph_pin_atom_net(pb_id, pb_graph_pin, atom_net); diff --git a/openfpga/src/repack/physical_pb.cpp b/openfpga/src/repack/physical_pb.cpp index 74894293a..4650d7d0d 100644 --- a/openfpga/src/repack/physical_pb.cpp +++ b/openfpga/src/repack/physical_pb.cpp @@ -81,6 +81,17 @@ AtomNetId PhysicalPb::pb_graph_pin_atom_net(const PhysicalPbId& pb, return AtomNetId::INVALID(); } +bool PhysicalPb::is_wire_lut_output(const PhysicalPbId& pb, + const t_pb_graph_pin* pb_graph_pin) const { + VTR_ASSERT(true == valid_pb_id(pb)); + if (wire_lut_outputs_[pb].find(pb_graph_pin) != wire_lut_outputs_[pb].end()) { + /* Find it, return the status */ + return wire_lut_outputs_[pb].at(pb_graph_pin); + } + /* Not found, return false */ + return false; +} + std::map PhysicalPb::truth_tables(const PhysicalPbId& pb) const { VTR_ASSERT(true == valid_pb_id(pb)); return truth_tables_[pb]; @@ -110,6 +121,7 @@ PhysicalPbId PhysicalPb::create_pb(const t_pb_graph_node* pb_graph_node) { pb_graph_nodes_.push_back(pb_graph_node); atom_blocks_.emplace_back(); pin_atom_nets_.emplace_back(); + wire_lut_outputs_.emplace_back(); child_pbs_.emplace_back(); parent_pbs_.emplace_back(); @@ -182,6 +194,18 @@ void PhysicalPb::set_pb_graph_pin_atom_net(const PhysicalPbId& pb, pin_atom_nets_[pb][pb_graph_pin] = atom_net; } +void PhysicalPb::set_wire_lut_output(const PhysicalPbId& pb, + const t_pb_graph_pin* pb_graph_pin, + const bool& wire_lut_output) { + VTR_ASSERT(true == valid_pb_id(pb)); + if (wire_lut_outputs_[pb].end() != wire_lut_outputs_[pb].find(pb_graph_pin)) { + VTR_LOG_WARN("Overwrite pb_graph_pin '%s[%d]' status on wire LUT output\n", + pb_graph_pin->port->name, pb_graph_pin->pin_number); + } + + wire_lut_outputs_[pb][pb_graph_pin] = wire_lut_output; +} + /****************************************************************************** * Private validators/invalidators ******************************************************************************/ diff --git a/openfpga/src/repack/physical_pb.h b/openfpga/src/repack/physical_pb.h index 11559da6b..6d8d2ba3b 100644 --- a/openfpga/src/repack/physical_pb.h +++ b/openfpga/src/repack/physical_pb.h @@ -50,6 +50,8 @@ class PhysicalPb { std::vector atom_blocks(const PhysicalPbId& pb) const; AtomNetId pb_graph_pin_atom_net(const PhysicalPbId& pb, const t_pb_graph_pin* pb_graph_pin) const; + bool is_wire_lut_output(const PhysicalPbId& pb, + const t_pb_graph_pin* pb_graph_pin) const; std::map truth_tables(const PhysicalPbId& pb) const; std::vector mode_bits(const PhysicalPbId& pb) const; public: /* Public mutators */ @@ -67,6 +69,9 @@ class PhysicalPb { void set_pb_graph_pin_atom_net(const PhysicalPbId& pb, const t_pb_graph_pin* pb_graph_pin, const AtomNetId& atom_net); + void set_wire_lut_output(const PhysicalPbId& pb, + const t_pb_graph_pin* pb_graph_pin, + const bool& wire_lut_output); public: /* Public validators/invalidators */ bool valid_pb_id(const PhysicalPbId& pb_id) const; bool empty() const; @@ -76,6 +81,7 @@ class PhysicalPb { vtr::vector names_; vtr::vector> atom_blocks_; vtr::vector> pin_atom_nets_; + vtr::vector> wire_lut_outputs_; /* Child pbs are organized as [0..num_child_pb_types-1][0..child_pb_type->num_pb-1] */ vtr::vector>> child_pbs_; diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 2d0b2c3e8..39697f100 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -117,15 +117,21 @@ int find_pb_route_remapped_source_pb_pin(const t_pb* pb, for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) { /* Bypass unused pins */ - if ((0 == pb->pb_route.count(pin)) || (AtomNetId::INVALID() == pb->pb_route[pin].atom_net_id)) { + if ((0 == pb->pb_route.count(pin)) || (AtomNetId::INVALID() == pb->pb_route.at(pin).atom_net_id)) { continue; } /* Get the driver pb pin id, it must be valid */ - if (atom_net_id != pb->pb_route[pin].atom_net_id) { + if (atom_net_id != pb->pb_route.at(pin).atom_net_id) { continue; } - /* Only care the pin that shares the same parent_node as source_pb_pin */ - if (source_pb_pin->parent_node == pb->pb_route[pin].pb_graph_pin->parent_node) { + /* Only care the pin has the same parent port as source_pb_pin + * Due to that the source_pb_pin may be swapped during routing + * the pb_route is out-of-date + * TODO: should update pb_route by post routing results + * On the other side, the swapping can only happen between equivalent pins + * in a port. So the port must match here! + */ + if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) { pb_route_indices.push_back(pin); } } @@ -272,17 +278,20 @@ void add_lb_router_nets(LbRouter& lb_router, VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size()); /* Printf for debugging only, may be enabled if verbose is enabled - VTR_LOG("Pb route for Net %s:\n", - atom_ctx.nlist.net_name(atom_net_id).c_str()); - VTR_LOG("Source node:\n\t%s -> %s\n", - source_pb_pin->to_string().c_str(), - source_pb_pin->to_string().c_str()); - VTR_LOG("Sink nodes:\n"); - for (t_pb_graph_pin* sink_pb_pin : sink_pb_graph_pins) { - VTR_LOG("\t%s\n", - sink_pb_pin->to_string().c_str()); - } */ + VTR_LOGV(verbose, + "Pb route for Net %s:\n", + atom_ctx.nlist.net_name(atom_net_id).c_str()); + VTR_LOGV(verbose, + "Source node:\n\t%s -> %s\n", + source_pb_pin->to_string().c_str(), + source_pb_pin->to_string().c_str()); + VTR_LOGV(verbose, "Sink nodes:\n"); + for (t_pb_graph_pin* sink_pb_pin : sink_pb_graph_pins) { + VTR_LOGV(verbose, + "\t%s\n", + sink_pb_pin->to_string().c_str()); + } /* Add the net */ add_lb_router_net_to_route(lb_router, lb_rr_graph, @@ -335,17 +344,20 @@ void add_lb_router_nets(LbRouter& lb_router, VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size()); /* Printf for debugging only, may be enabled if verbose is enabled - VTR_LOG("Pb route for Net %s:\n", - atom_ctx.nlist.net_name(atom_net_id).c_str()); - VTR_LOG("Source node:\n\t%s -> %s\n", - source_pb_pin->to_string().c_str(), - physical_source_pb_pin->to_string().c_str()); - VTR_LOG("Sink nodes:\n"); - for (t_pb_graph_pin* sink_pb_pin : sink_pb_graph_pins) { - VTR_LOG("\t%s\n", - sink_pb_pin->to_string().c_str()); - } */ + VTR_LOGV(verbose, + "Pb route for Net %s:\n", + atom_ctx.nlist.net_name(atom_net_id).c_str()); + VTR_LOGV(verbose, + "Source node:\n\t%s -> %s\n", + source_pb_pin->to_string().c_str(), + physical_source_pb_pin->to_string().c_str()); + VTR_LOGV(verbose, "Sink nodes:\n"); + for (t_pb_graph_pin* sink_pb_pin : sink_pb_graph_pins) { + VTR_LOGV(verbose, + "\t%s\n", + sink_pb_pin->to_string().c_str()); + } /* Add the net */ add_lb_router_net_to_route(lb_router, lb_rr_graph, @@ -423,7 +435,8 @@ void repack_cluster(const AtomContext& atom_ctx, clustering_ctx.clb_nlist.block_pb(block_id), clustering_ctx.clb_nlist.block_pb(block_id)->pb_route, atom_ctx, - device_annotation); + device_annotation, + verbose); /* Save routing results */ save_lb_router_results_to_physical_pb(phy_pb, lb_router, lb_rr_graph); VTR_LOGV(verbose, "Saved results in physical pb\n"); diff --git a/openfpga/src/utils/lut_utils.cpp b/openfpga/src/utils/lut_utils.cpp index ca3ac343e..35f613c73 100644 --- a/openfpga/src/utils/lut_utils.cpp +++ b/openfpga/src/utils/lut_utils.cpp @@ -473,6 +473,29 @@ std::vector build_frac_lut_bitstream(const CircuitLibrary& circuit_lib, VTR_ASSERT(bitstream_offset < lut_bitstream.size()); VTR_ASSERT(bitstream_offset + length_of_temp_bitstream_to_copy <= lut_bitstream.size()); + /* Print debug information + bool verbose = true; + VTR_LOGV(verbose, "Full truth table\n"); + for (const std::string& tt_line : truth_table_to_string(element.second)) { + VTR_LOGV(verbose, "\t%s\n", tt_line.c_str()); + } + VTR_LOGV(verbose, "\n"); + + VTR_LOGV(verbose, "Bitstream (size = %ld)\n", temp_bitstream.size()); + for (const bool& bit : temp_bitstream) { + if (true == bit) { + VTR_LOGV(verbose, "1"); + } else { + VTR_ASSERT(false == bit); + VTR_LOGV(verbose, "0"); + } + } + VTR_LOGV(verbose, "\n"); + + VTR_LOGV(verbose, "Bitstream offset = %d\n", bitstream_offset); + VTR_LOGV(verbose, "Bitstream length to be used = %d\n", length_of_temp_bitstream_to_copy); + */ + /* Copy to the segment of bitstream */ for (size_t bit = bitstream_offset; bit < bitstream_offset + length_of_temp_bitstream_to_copy; ++bit) { lut_bitstream[bit] = temp_bitstream[bit]; diff --git a/openfpga/src/utils/pb_type_utils.h b/openfpga/src/utils/pb_type_utils.h index 6a4dd91be..5d23f23bc 100644 --- a/openfpga/src/utils/pb_type_utils.h +++ b/openfpga/src/utils/pb_type_utils.h @@ -17,6 +17,15 @@ /* begin namespace openfpga */ namespace openfpga { +/* Constants */ + +/* Mode index of a LUT pb_type + * Mode 0 is the wire mode + * Mode 1 is the lut mode + */ +constexpr int VPR_PB_TYPE_WIRE_MODE = 0; +constexpr int VPR_PB_TYPE_LUT_MODE = 1; + bool is_primitive_pb_type(t_pb_type* pb_type); bool is_root_pb_type(t_pb_type* pb_type); diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp index 93fbba992..129784575 100644 --- a/openfpga/src/utils/physical_pb_utils.cpp +++ b/openfpga/src/utils/physical_pb_utils.cpp @@ -132,6 +132,16 @@ void update_primitive_physical_pb_pin_atom_net(PhysicalPb& phy_pb, t_pb_graph_pin* physical_pb_graph_pin = device_annotation.physical_pb_graph_pin(pb_graph_pin); VTR_ASSERT(nullptr != physical_pb_graph_pin); + /* Print info to help debug + bool verbose = true; + VTR_LOGV(verbose, + "\nSynchronize net '%lu' to physical pb_graph_pin '%s.%s[%d]'\n", + size_t(atom_net), + pb_graph_pin->parent_node->pb_type->name, + pb_graph_pin->port->name, + pb_graph_pin->pin_number); + */ + /* Check if the pin has been mapped to a net. * If yes, the atom net must be the same */ @@ -155,6 +165,7 @@ void synchronize_primitive_physical_pb_atom_nets(PhysicalPb& phy_pb, const AtomBlockId& atom_blk, const VprDeviceAnnotation& device_annotation) { /* Iterate over all the ports: input, output and clock */ + for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) { for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) { /* Port exists (some LUTs may have no input and hence no port in the atom netlist) */ @@ -219,6 +230,46 @@ void synchronize_primitive_physical_pb_atom_nets(PhysicalPb& phy_pb, } } +/************************************************************************ + * Reach this function, the primitive pb should be + * - linked to a LUT pb_type + * - operating in the wire mode of a LUT + * + * Note: this function will not check the prequistics here + * Users must be responsible for this!!! + * + * This function will find the physical pb_graph_pin for each output + * of the pb_graph node and mark in the physical_pb database + * as driven by an wired LUT + ***********************************************************************/ +static +void mark_physical_pb_wired_lut_outputs(PhysicalPb& phy_pb, + const PhysicalPbId& primitive_pb, + const t_pb_graph_node* pb_graph_node, + const VprDeviceAnnotation& device_annotation, + const bool& verbose) { + + for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) { + t_pb_graph_pin* pb_graph_pin = &(pb_graph_node->output_pins[iport][ipin]); + + /* Find the physical pb_graph_pin */ + t_pb_graph_pin* physical_pb_graph_pin = device_annotation.physical_pb_graph_pin(pb_graph_pin); + VTR_ASSERT(nullptr != physical_pb_graph_pin); + + /* Print debug info */ + VTR_LOGV(verbose, + "Mark physical pb_graph pin '%s.%s[%d]' as wire LUT output\n", + physical_pb_graph_pin->parent_node->pb_type->name, + physical_pb_graph_pin->port->name, + physical_pb_graph_pin->pin_number); + + /* Label the pins in physical_pb as driven by wired LUT*/ + phy_pb.set_wire_lut_output(primitive_pb, physical_pb_graph_pin, true); + } + } +} + /************************************************************************ * Synchronize mapping results from an operating pb to a physical pb ***********************************************************************/ @@ -226,7 +277,8 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, const t_pb* op_pb, const t_pb_routes& pb_route, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation) { + const VprDeviceAnnotation& device_annotation, + const bool& verbose) { t_pb_graph_node* pb_graph_node = op_pb->pb_graph_node; t_pb_type* pb_type = pb_graph_node->pb_type; @@ -265,7 +317,55 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, &(op_pb->child_pbs[ipb][jpb]), pb_route, atom_ctx, - device_annotation); + device_annotation, + verbose); + } else { + /* Some pb may be used just in routing purpose, find out the output nets */ + /* The following code is inspired by output_cluster.cpp */ + bool is_used = false; + t_pb_type* child_pb_type = &(mapped_mode->pb_type_children[ipb]); + + /* Bypass non-primitive pb_type, we care only the LUT pb_type */ + if (false == is_primitive_pb_type(child_pb_type)) { + continue; + } + + int port_index = 0; + t_pb_graph_node* child_pb_graph_node = &(pb_graph_node->child_pb_graph_nodes[op_pb->mode][ipb][jpb]); + + for (int k = 0; k < child_pb_type->num_ports && !is_used; k++) { + if (OUT_PORT == child_pb_type->ports[k].type) { + for (int m = 0; m < child_pb_type->ports[k].num_pins; m++) { + int node_index = child_pb_graph_node->output_pins[port_index][m].pin_count_in_cluster; + if (pb_route.count(node_index) && pb_route[node_index].atom_net_id) { + is_used = true; + break; + } + } + port_index++; + } + } + /* Identify output pb_graph_pin that is driven by a wired LUT + * Without this function, physical Look-Up Table build-up will cause errors + * and bitstream will be incorrect!!! + */ + if (true == is_used) { + VTR_ASSERT(LUT_CLASS == child_pb_type->class_type); + + t_pb_graph_node* physical_pb_graph_node = device_annotation.physical_pb_graph_node(child_pb_graph_node); + VTR_ASSERT(nullptr != physical_pb_graph_node); + /* Find the physical pb */ + const PhysicalPbId& physical_pb = phy_pb.find_pb(physical_pb_graph_node); + VTR_ASSERT(true == phy_pb.valid_pb_id(physical_pb)); + + /* Set the mode bits */ + phy_pb.set_mode_bits(physical_pb, device_annotation.pb_type_mode_bits(child_pb_type)); + + mark_physical_pb_wired_lut_outputs(phy_pb, physical_pb, + child_pb_graph_node, + device_annotation, + verbose); + } } } } diff --git a/openfpga/src/utils/physical_pb_utils.h b/openfpga/src/utils/physical_pb_utils.h index 0e8bb71df..227feec6c 100644 --- a/openfpga/src/utils/physical_pb_utils.h +++ b/openfpga/src/utils/physical_pb_utils.h @@ -28,7 +28,8 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, const t_pb* op_pb, const t_pb_routes& pb_route, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation); + const VprDeviceAnnotation& device_annotation, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga index e14811f49..20a75a661 100644 --- a/openfpga/test_script/and_k6_frac.openfpga +++ b/openfpga/test_script/and_k6_frac.openfpga @@ -34,7 +34,7 @@ repack #--verbose build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml # Build fabric-dependent bitstream -build_fabric_bitstream --verbose +build_fabric_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/and.bitstream # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga new file mode 100644 index 000000000..66b4c12fa --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga @@ -0,0 +1,61 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml index f9065d437..fcbc20437 100644 --- a/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml +++ b/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml @@ -54,7 +54,7 @@ - + @@ -137,7 +137,7 @@ - + @@ -197,7 +197,7 @@ --> - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 180e-12 + 180e-12 + 180e-12 + 180e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 229e-12 + 229e-12 + 229e-12 + 229e-12 + 229e-12 + 229e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml new file mode 100755 index 000000000..d4a4104af --- /dev/null +++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml @@ -0,0 +1,1542 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb_spypad.sc_in clb_spypad.cin clb_spypad.cin_trick clb_spypad.regin clb_spypad.clk + clb_spypad.I0[9:0] clb_spypad.I1[9:0] clb_spypad.O[9:0] + clb_spypad.cout clb_spypad.cout_copy clb_spypad.sc_out clb_spypad.regout clb_spypad.I2[9:0] clb_spypad.I3[9:0] clb_spypad.O[19:10] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + 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+ 180e-12 + 180e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 229e-12 + 229e-12 + 229e-12 + 229e-12 + 229e-12 + 229e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 180e-12 + 180e-12 + 180e-12 + 180e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 229e-12 + 229e-12 + 229e-12 + 229e-12 + 229e-12 + 229e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml new file mode 100755 index 000000000..15281812f --- /dev/null +++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml @@ -0,0 +1,802 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + memory.clk + memory.waddr memory.d_in[15:0] memory.wen memory.d_out[15:0] + memory.raddr memory.d_in[31:16] memory.ren memory.d_out[31:16] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 193e-12 + 193e-12 + 193e-12 + 193e-12 + 193e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 161e-12 + 161e-12 + 161e-12 + 161e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 230e-12 + 230e-12 + 230e-12 + 230e-12 + 230e-12 + 230e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/and.v b/openfpga_flow/benchmarks/micro_benchmark/and.v deleted file mode 100644 index 876f1c6fe..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/and.v +++ /dev/null @@ -1,14 +0,0 @@ -`timescale 1ns / 1ps - -module top( - a, - b, - c); - -input wire a; -input wire b; -output wire c; - -assign c = a & b; - -endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/and.act b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/and.act rename to openfpga_flow/benchmarks/micro_benchmark/and2/and2.act diff --git a/openfpga_flow/benchmarks/micro_benchmark/and.blif b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif similarity index 80% rename from openfpga_flow/benchmarks/micro_benchmark/and.blif rename to openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif index 67d978741..d13bdc564 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/and.blif +++ b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif @@ -1,4 +1,4 @@ -.model top +.model and2 .inputs a b .outputs c diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v new file mode 100644 index 000000000..a23293c58 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v @@ -0,0 +1,18 @@ +///////////////////////////////////////// +// Functionality: 2-input AND +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module and2( + a, + b, + c); + +input wire a; +input wire b; +output wire c; + +assign c = a & b; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch.act b/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/and_latch.act rename to openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch.blif b/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif similarity index 52% rename from openfpga_flow/benchmarks/micro_benchmark/and_latch.blif rename to openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif index dbd863d9c..96450e30a 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/and_latch.blif +++ b/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif @@ -1,5 +1,5 @@ -# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020 -.model top +# Benchmark "and2_latch" written by ABC on Wed Mar 11 10:36:28 2020 +.model and2_latch .inputs a b clk .outputs c d diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v b/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v new file mode 100644 index 000000000..135454daa --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v @@ -0,0 +1,29 @@ +///////////////////////////////////////// +// Functionality: 2-input AND with clocked +// and combinational outputs +// Author: Xifan Tang +//////////////////////////////////////// + +`timescale 1ns / 1ps + +module and2_latch( + a, + b, + clk, + c, + d); + +input wire clk; + +input wire a; +input wire b; +output wire c; +output reg d; + +assign c = a & b; + +always @(posedge clk) begin + d <= c; +end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch.v b/openfpga_flow/benchmarks/micro_benchmark/and_latch.v deleted file mode 100644 index 893cdf7a4..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/and_latch.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns / 1ps - -module top( - clk, - a, - b, - c, - d); - -input wire clk; - -input wire a; -input wire b; -output wire c; -output reg d; - -assign c = a & b; - -always @(posedge clk) begin - d <= c; -end - -endmodule diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml index de0602e1e..c3385e96c 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml @@ -146,11 +146,11 @@ - + - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml new file mode 100644 index 000000000..8d2aadaeb --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -0,0 +1,289 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml new file mode 100644 index 000000000..4939b2dc0 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -0,0 +1,373 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf index 4d5f90d67..e11da844f 100644 --- a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf index aeffa9a86..4996f42e2 100644 --- a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf index 53cc5407c..5cfc3ce57 100644 --- a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf @@ -22,12 +22,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf index 7415b96ab..79781a758 100644 --- a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf index 7f1f370c6..f2777f7ee 100644 --- a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf index 348d11cde..5e9533e36 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf index 29f1ac4b0..1b76cb3e9 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf index e1e85366b..ac398aa4c 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf index bb15c4c43..2879e95ed 100644 --- a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf index a52d2f515..a69c1107e 100644 --- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf @@ -21,13 +21,18 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +# Modelsim is ok with this but icarus fails due to poor support on timing and looping +#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v -bench0_chan_width = 300 +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +bench1_top = and2_latch +bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act +bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf index f9fbc97f2..c0198598e 100644 --- a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf index 9c10e2783..21751cc7f 100644 --- a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf index 2d08de621..0f4727657 100644 --- a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf @@ -32,12 +32,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf index a3f9081d9..8ae3286c5 100644 --- a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf index 8ed4998db..190acfda7 100644 --- a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf new file mode 100644 index 000000000..f2a92e6b9 --- /dev/null +++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf @@ -0,0 +1,133 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif +# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif +# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file +bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif +bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif +bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif +# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file +bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif +bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif +bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif +bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif +bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif +bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif +bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif +# Passed +#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif +bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif +bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif +bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif +bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif +bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif + +[SYNTHESIS_PARAM] +# Benchmark alu4 +bench0_top = alu4 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v +# Benchmark apex2 +bench1_top = apex2 +bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act +bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v +# Benchmark apex4 +bench2_top = apex4 +bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act +bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v +# Benchmark bigkey +bench3_top = bigkey +bench3_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act +bench3_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v +# Benchmark clma +bench4_top = clma +bench4_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act +bench4_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v +# Benchmark des +bench5_top = des +bench5_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.act +bench5_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.v +# Benchmark diffeq +bench6_top = diffeq +bench6_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act +bench6_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v +# Benchmark dsip +bench7_top = dsip +bench7_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act +bench7_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v +# Benchmark elliptic +bench8_top = elliptic +bench8_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act +bench8_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v +# Benchmark ex1010 +bench9_top = ex1010 +bench9_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act +bench9_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v +# Benchmark ex5p +bench10_top = ex5p +bench10_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act +bench10_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v +# Benchmark frisc +bench11_top = frisc +bench11_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act +bench11_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v +# Benchmark misex3 +bench12_top = misex3 +bench12_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act +bench12_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v +# Benchmark pdc +bench13_top = pdc +bench13_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act +bench13_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v +# Benchmark s298 +bench14_top = s298 +bench14_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act +bench14_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v +# Benchmark s38417 +bench15_top = s38417 +bench15_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act +bench15_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v +# Benchmark s38584 +bench16_top = s38584 +bench16_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act +bench16_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v +# Benchmark seq +bench17_top = seq +bench17_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act +bench17_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v +# Benchmark spla +bench18_top = spla +bench18_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act +bench18_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v +# Benchmark tseng +bench19_top = tseng +bench19_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act +bench19_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf index 6ad9d0db0..60df151e7 100644 --- a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf index 658e328c0..3f8b56582 100644 --- a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf b/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf new file mode 100644 index 000000000..4216a7482 --- /dev/null +++ b/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +bench1_top = and2_latch +bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act +bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf new file mode 100644 index 000000000..e093b2b53 --- /dev/null +++ b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf index 4ea65822f..7dcf88915 100644 --- a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf @@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/vpr/src/base/read_activity.cpp b/vpr/src/base/read_activity.cpp index 41cc86a21..821fc4672 100644 --- a/vpr/src/base/read_activity.cpp +++ b/vpr/src/base/read_activity.cpp @@ -19,8 +19,8 @@ static bool add_activity_to_net(const AtomNetlist& netlist, std::unordered_map