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[core] code format

This commit is contained in:
tangxifan 2024-05-20 13:41:35 -07:00
parent 8c3da74835
commit ca6e2f9831
2 changed files with 19 additions and 12 deletions
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18
libs/libarchopenfpga/src/read_xml_routing_circuit.cpp
View File

@ -278,10 +278,11 @@ ArchDirect read_xml_direct_circuit(pugi::xml_node& Node,
e_direct_type direct_type = string_to_direct_type(direct_type_name); e_direct_type direct_type = string_to_direct_type(direct_type_name);
if (e_direct_type::NUM_DIRECT_TYPES == direct_type) { if (e_direct_type::NUM_DIRECT_TYPES == direct_type) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_direct), archfpga_throw(
"Direct type '%s' is not support! Acceptable values are " loc_data.filename_c_str(), loc_data.line(xml_direct),
"[inner_column_or_row|part_of_cb|inter_column|inter_row]\n", "Direct type '%s' is not support! Acceptable values are "
direct_type_name.c_str()); "[inner_column_or_row|part_of_cb|inter_column|inter_row]\n",
direct_type_name.c_str());
} }
arch_direct.set_type(direct, direct_type); arch_direct.set_type(direct, direct_type);
@ -290,14 +291,17 @@ ArchDirect read_xml_direct_circuit(pugi::xml_node& Node,
std::string direct_model_name = std::string direct_model_name =
get_attribute(xml_direct, "circuit_model_name", loc_data).as_string(); get_attribute(xml_direct, "circuit_model_name", loc_data).as_string();
/* If a direct connection is part of a connection block, the circuit model should be a MUX */ /* If a direct connection is part of a connection block, the circuit model
* should be a MUX */
e_circuit_model_type expected_circuit_model_type = CIRCUIT_MODEL_WIRE; e_circuit_model_type expected_circuit_model_type = CIRCUIT_MODEL_WIRE;
if (arch_direct.type(direct) == e_direct_type::PART_OF_CB) { if (arch_direct.type(direct) == e_direct_type::PART_OF_CB) {
VTR_LOG("Direct '%s' will modelled as part of a connection block.\n", direct_name.c_str()); VTR_LOG("Direct '%s' will modelled as part of a connection block.\n",
direct_name.c_str());
expected_circuit_model_type = CIRCUIT_MODEL_MUX; expected_circuit_model_type = CIRCUIT_MODEL_MUX;
} }
CircuitModelId direct_model = find_routing_circuit_model( CircuitModelId direct_model = find_routing_circuit_model(
xml_direct, loc_data, circuit_lib, direct_model_name, expected_circuit_model_type); xml_direct, loc_data, circuit_lib, direct_model_name,
expected_circuit_model_type);
arch_direct.set_circuit_model(direct, direct_model); arch_direct.set_circuit_model(direct, direct_model);
/* The following syntax is only available for inter-column/row */ /* The following syntax is only available for inter-column/row */

13
openfpga/src/annotation/annotate_rr_graph.cpp
View File

@ -704,16 +704,20 @@ static void annotate_direct_circuit_models(
} }
/* Check the circuit model type */ /* Check the circuit model type */
if (openfpga_arch.arch_direct.type(direct_id) != e_direct_type::PART_OF_CB && CIRCUIT_MODEL_WIRE != if (openfpga_arch.arch_direct.type(direct_id) !=
openfpga_arch.circuit_lib.model_type(circuit_model)) { e_direct_type::PART_OF_CB &&
CIRCUIT_MODEL_WIRE !=
openfpga_arch.circuit_lib.model_type(circuit_model)) {
VTR_LOG_ERROR( VTR_LOG_ERROR(
"Require circuit model type '%s' for a direct connection '%s'!\nPlease " "Require circuit model type '%s' for a direct connection '%s'!\nPlease "
"check your OpenFPGA architecture XML!\n", "check your OpenFPGA architecture XML!\n",
CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_WIRE], direct_name.c_str()); CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_WIRE], direct_name.c_str());
exit(1); exit(1);
} }
if (openfpga_arch.arch_direct.type(direct_id) == e_direct_type::PART_OF_CB && CIRCUIT_MODEL_MUX != if (openfpga_arch.arch_direct.type(direct_id) ==
openfpga_arch.circuit_lib.model_type(circuit_model)) { e_direct_type::PART_OF_CB &&
CIRCUIT_MODEL_MUX !=
openfpga_arch.circuit_lib.model_type(circuit_model)) {
VTR_LOG_ERROR( VTR_LOG_ERROR(
"Require circuit model type '%s' for a direct connection '%s'!\nPlease " "Require circuit model type '%s' for a direct connection '%s'!\nPlease "
"check your OpenFPGA architecture XML!\n", "check your OpenFPGA architecture XML!\n",
@ -721,7 +725,6 @@ static void annotate_direct_circuit_models(
exit(1); exit(1);
} }
/* Now update the device annotation */ /* Now update the device annotation */
vpr_device_annotation.add_direct_annotation(idirect, direct_id); vpr_device_annotation.add_direct_annotation(idirect, direct_id);
VTR_LOGV(verbose_output, VTR_LOGV(verbose_output,