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[Arch] Add flagship architecture with 8-clock

This commit is contained in:
tangxifan 2021-02-22 15:01:18 -07:00
parent 2e2b1cb6e7
commit ca135f3325
2 changed files with 16 additions and 3 deletions
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4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
View File

@ -318,9 +318,9 @@
<!-- Bind the 512x64 single port RAM to the physical implementation -->
<pb_type name="memory[mem_512x64_sp].mem_512x64_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
<port name="addr" physical_mode_port="addr1[0:8]"/>
<port name="data" physical_mode_port="data1 data2" physical_mode_pin_initial_offset="-32 -32"/>
<port name="data" physical_mode_port="data1 data2" physical_mode_pin_initial_offset="0 -32"/>
<port name="we" physical_mode_port="we1"/>
<port name="out" physical_mode_port="out1 out2" physical_mode_pin_initial_offset="-32 -32"/>
<port name="out" physical_mode_port="out1 out2" physical_mode_pin_initial_offset="0 -32"/>
<port name="clk" physical_mode_port="clk"/>
</pb_type>
<!-- Bind the 1024x32 single port RAM to the physical implementation -->

15
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_GlobalTile8Clk_40nm.xml
View File

@ -207,7 +207,7 @@
<fc_override port_name="cout" fc_type="frac" fc_val="0"/>
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
</fc>
<!-- Highly recommand to customize pin location when direct connection is used!!! -->
<!-- Highly recommand to customize pin location when direct connection is used!!! -->
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left">clb.clk</loc>
@ -273,6 +273,19 @@
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
</auto_layout>
<fixed_layout name="32x32" width="34" height="34">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
<!--Column of 'mult_36' with 'EMPTY' blocks wherever a 'mult_36' does not fit. Vertical offset by 1 for perimeter.-->
<col type="mult_36" startx="6" starty="1" repeatx="8" priority="20"/>
<col type="EMPTY" startx="6" repeatx="8" starty="1" priority="19"/>
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
</fixed_layout>
</layout>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM