diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c index 83fcf2121..a202513eb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c @@ -1332,25 +1332,6 @@ t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, return ret; } -/******************************************************************** - * Add the port-to-port mapping between a pb_type and its linked circuit model - * This function is mainly used to create instance of the module for a pb_type - *******************************************************************/ -void generate_pb_type_circuit_port2port_name_map(std::map& port2port_name_map, - t_pb_type* cur_pb_type, - const CircuitLibrary& circuit_lib) { - for (int iport = 0; iport < cur_pb_type->num_ports; ++iport) { - t_port* pb_type_port = &(cur_pb_type->ports[iport]); - /* Must have a linked circuit model port */ - VTR_ASSERT( CircuitPortId::INVALID() != pb_type_port->circuit_model_port); - std::string module_port_name = circuit_lib.port_lib_name(pb_type_port->circuit_model_port); - /* Generate the module port name of pb_type */ - BasicPort instance_port(generate_pb_type_port_name(pb_type_port), circuit_lib.port_size(pb_type_port->circuit_model_port)); - /* Create the port of primitive model */ - port2port_name_map[module_port_name] = instance_port; - } -} - /******************************************************************** * Return a list of ports of a pb_type which matches the ports defined * in its linked circuit model diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index d7c969efa..954984e89 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -106,10 +106,6 @@ void map_clb_pins_to_pb_graph_pins(); t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, t_spice_model_port* spice_model_port); -void generate_pb_type_circuit_port2port_name_map(std::map& port2port_name_map, - t_pb_type* cur_pb_type, - const CircuitLibrary& circuit_lib); - std::vector find_pb_type_ports_match_circuit_model_port_type(t_pb_type* pb_type, enum e_spice_model_port_type port_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 658bddee8..ea1b034ad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -6,6 +6,7 @@ #include #include +#include "util.h" #include "vtr_assert.h" #include "spice_types.h" @@ -326,3 +327,73 @@ bool module_net_include_local_short_connection(const ModuleManager& module_manag return contain_module_input & contain_module_output; } + +/******************************************************************** + * Add the port-to-port connection between a pb_type and its linked circuit model + * This function is mainly used to create instance of the module for a pb_type + * + * Note: this function SHOULD be called after the pb_type_module is created + * and its child module is created! + *******************************************************************/ +void add_primitive_pb_type_module_nets(ModuleManager& module_manager, + const ModuleId& pb_type_module, + const ModuleId& child_module, + const size_t& child_instance_id, + const CircuitLibrary& circuit_lib, + t_pb_type* cur_pb_type) { + for (int iport = 0; iport < cur_pb_type->num_ports; ++iport) { + t_port* pb_type_port = &(cur_pb_type->ports[iport]); + /* Must have a linked circuit model port */ + VTR_ASSERT( CircuitPortId::INVALID() != pb_type_port->circuit_model_port); + + /* Find the source port in pb_type module */ + /* Get the src module port id */ + ModulePortId src_module_port_id = module_manager.find_module_port(pb_type_module, generate_pb_type_port_name(pb_type_port)); + VTR_ASSERT(ModulePortId::INVALID() != src_module_port_id); + BasicPort src_port = module_manager.module_port(pb_type_module, src_module_port_id); + + /* Get the des module port id */ + std::string des_module_port_name = circuit_lib.port_lib_name(pb_type_port->circuit_model_port); + ModulePortId des_module_port_id = module_manager.find_module_port(child_module, des_module_port_name); + VTR_ASSERT(ModulePortId::INVALID() != des_module_port_id); + BasicPort des_port = module_manager.module_port(child_module, des_module_port_id); + + /* Port size must match */ + if (src_port.get_width() != des_port.get_width()) + VTR_ASSERT(src_port.get_width() == des_port.get_width()); + + /* For each pin, generate the nets. + * For non-output ports (input ports, inout ports and clock ports), + * src_port is the source of the net + * For output ports + * src_port is the sink of the net + */ + switch (pb_type_port->type) { + case IN_PORT: + case INOUT_PORT: + for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(pb_type_module); + /* Add net source */ + module_manager.add_module_net_source(pb_type_module, net, pb_type_module, 0, src_module_port_id, src_port.pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(pb_type_module, net, child_module, child_instance_id, des_module_port_id, des_port.pins()[pin_id]); + } + break; + case OUT_PORT: + for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(pb_type_module); + /* Add net source */ + module_manager.add_module_net_sink(pb_type_module, net, pb_type_module, 0, src_module_port_id, src_port.pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_source(pb_type_module, net, child_module, child_instance_id, des_module_port_id, des_port.pins()[pin_id]); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid port of pb_type!\n", + __FILE__, __LINE__); + exit(1); + } + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 9bcd5b154..4bfa2125c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -49,4 +49,10 @@ bool module_net_is_local_wire(const ModuleManager& module_manager, bool module_net_include_local_short_connection(const ModuleManager& module_manager, const ModuleId& module_id, const ModuleNetId& module_net); +void add_primitive_pb_type_module_nets(ModuleManager& module_manager, + const ModuleId& pb_type_module, + const ModuleId& child_module, + const size_t& child_instance_id, + const CircuitLibrary& circuit_lib, + t_pb_type* cur_pb_type); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index dd6822c35..9151fafc7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -27,6 +27,7 @@ #include "verilog_global.h" #include "verilog_utils.h" #include "verilog_writer_utils.h" +#include "verilog_module_writer.h" #include "verilog_grid.h" /******************************************************************** @@ -145,47 +146,22 @@ void print_verilog_primitive_block(std::fstream& fp, num_config_bits); } - /* Print the module definition for the top-level Verilog module of physical block */ - print_verilog_module_declaration(fp, module_manager, primitive_module); - /* Finish printing ports */ - /* Find the module id in the module manager */ ModuleId logic_module = module_manager.find_module(circuit_lib.model_name(primitive_model)); VTR_ASSERT(ModuleId::INVALID() != logic_module); size_t logic_instance_id = module_manager.num_instance(primitive_module, logic_module); - - /* Local wires for memory configurations */ - print_verilog_comment(fp, std::string("---- BEGIN local configuration bus ----")); - print_verilog_local_config_bus(fp, circuit_lib.model_name(primitive_model), cur_sram_orgz_info->type, logic_instance_id, num_config_bits); - print_verilog_comment(fp, std::string("---- END local configuration bus ----")); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* TODO: Instanciate the logic module */ - /* Create port-to-port map */ - std::map logic_port2port_name_map; - /* Link the logic model ports to pb_type ports */ - generate_pb_type_circuit_port2port_name_map(logic_port2port_name_map, primitive_pb_graph_node->pb_type, circuit_lib); - /* TODO: Link both regular and mode-select SRAM ports */ - - /* Print an instance of the logic Module */ - print_verilog_comment(fp, std::string("----- BEGIN Instanciation of " + circuit_lib.model_name(primitive_model) + " -----")); - print_verilog_module_instance(fp, module_manager, primitive_module, logic_module, logic_port2port_name_map, use_explicit_mapping); - print_verilog_comment(fp, std::string("----- END Instanciation of " + circuit_lib.model_name(primitive_model) + " -----")); - fp << std::endl; - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ + /* Add the logic module as a child of primitive module */ module_manager.add_child_module(primitive_module, logic_module); - /* Add an empty line as a splitter */ - fp << std::endl; + /* Add nets to connect the logic model ports to pb_type ports */ + add_primitive_pb_type_module_nets(module_manager, primitive_module, logic_module, logic_instance_id, circuit_lib, primitive_pb_graph_node->pb_type); - /* TODO: Instanciate associated memory module */ + /* TODO: add the associated memory module as a child of primitive module */ - /* Print an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(primitive_module)); + /* TODO: Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ + + /* TODO: write the verilog module */ + write_verilog_module_to_file(fp, module_manager, primitive_module, use_explicit_mapping); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index a5ab907b5..ea43f35e0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -13,12 +13,6 @@ #include "verilog_writer_utils.h" #include "verilog_module_writer.h" -/******************************************************************** - * Local constant variables for naming purpose - instance_port.set_name(VERILOG_MODULE_LOCAL_GND_WIRE_NAME); - *******************************************************************/ -constexpr char* VERILOG_MODULE_LOCAL_GND_WIRE_NAME = "VERILOG_CONSTANT_GND"; - /******************************************************************** * Name a net for a local wire for a verilog module * 1. If this is a local wire, name it after the __ @@ -254,12 +248,9 @@ void write_verilog_instance_to_file(std::fstream& fp, child_port_id, child_pin); BasicPort instance_port; if (ModuleNetId::INVALID() == net) { - /* For unused net: assign a constant 0 value - * TODO: make it flexible to select between 0 and 1 - */ - /* TODO: output a warning? This could be potential issues for Verilog netlists */ - instance_port.set_name(VERILOG_MODULE_LOCAL_GND_WIRE_NAME); - instance_port.set_width(1); + /* We give the same port name as child module, this case happens to global ports */ + instance_port.set_name(module_manager.module_port(child_module, child_port_id).get_name()); + instance_port.set_width(child_pin, child_pin); } else { /* Find the name for this child port */ instance_port = generate_verilog_port_for_module_net(module_manager, parent_module, net); @@ -303,9 +294,6 @@ void write_verilog_module_to_file(std::fstream& fp, /* Print an empty line as splitter */ fp << std::endl; - /* Print constant GND wires */ - BasicPort constant_gnd_local_wire(VERILOG_MODULE_LOCAL_GND_WIRE_NAME, 1); - fp << generate_verilog_port(VERILOG_PORT_WIRE, constant_gnd_local_wire) << ";" << std::endl; /* Print internal wires */ std::vector local_wires = find_verilog_module_local_wires(module_manager, module_id); for (BasicPort local_wire : local_wires) {