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[Arch] Patch openfpga architecture for ccff circuit model port requirement

This commit is contained in:
tangxifan 2021-01-04 17:15:50 -07:00
parent cc91a0aebd
commit c97a92d628
1 changed files with 1 additions and 2 deletions
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3
openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml
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@ -147,9 +147,8 @@
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="SI" size="1"/> <port type="input" prefix="SI" size="1"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="output" prefix="QN" size="1"/>
<port type="output" prefix="CFGQ" size="1"/>
<port type="output" prefix="CFGQN" size="1"/> <port type="output" prefix="CFGQN" size="1"/>
<port type="output" prefix="CFGQ" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">