diff --git a/openfpga/src/utils/rr_gsb_utils.cpp b/openfpga/src/utils/rr_gsb_utils.cpp
index 64445679f..b931a43a6 100644
--- a/openfpga/src/utils/rr_gsb_utils.cpp
+++ b/openfpga/src/utils/rr_gsb_utils.cpp
@@ -282,9 +282,6 @@ bool is_cb_node_mirror(const RRGraphView& rr_graph,
                        const e_side& node_side, 
                        const size_t& node_id) {
   /* Ensure rr_nodes are either the output of short-connection or multiplexer  */
-  RRNodeId node = base.get_ipin_node(node_side, node_id);
-  RRNodeId cand_node = cand.get_ipin_node(node_side, node_id);
-
   std::vector<RREdgeId> node_in_edges = base.get_ipin_node_in_edges(rr_graph, node_side, node_id);
   std::vector<RREdgeId> cand_node_in_edges = cand.get_ipin_node_in_edges(rr_graph, node_side, node_id);
   if (node_in_edges.size() != cand_node_in_edges.size()) {
diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing
index bb895cb73..657624796 160000
--- a/vtr-verilog-to-routing
+++ b/vtr-verilog-to-routing
@@ -1 +1 @@
-Subproject commit bb895cb73226336caff2eb49017ead3a3dc27f99
+Subproject commit 657624796fbdab8c69d14f788bd501a31ef35784