From c8da85cc2494cef25cc2adf9c02cb0faa011b01c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Mar 2022 10:51:55 +0800
Subject: [PATCH] [Doc] Update naming convention for OpenFPGA architecture
 files

---
 openfpga_flow/openfpga_arch/README.md | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md
index ed4a17815..36fb95acd 100644
--- a/openfpga_flow/openfpga_arch/README.md
+++ b/openfpga_flow/openfpga_arch/README.md
@@ -31,6 +31,8 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f
 - tree\_mux: If routing multiplexers are built with a tree-like structure
 - <feature_size>: The technology node which the delay numbers are extracted from.
 - powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
-- GlobalTile<Int>Clk: How many clocks are defined through global ports from physical tiles. <Int> is the number of clocks 
+- GlobalTile<Int>Clk<Pin>: How many clocks are defined through global ports from physical tiles.
+  * <Int> is the number of clocks 
+  * <Pin> When specified, multiple clocks are in separated pins with different names
 
 Other features are used in naming should be listed here.