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[Tool] Change routing module port naming to include architecture port names

This commit is contained in:
tangxifan 2021-03-14 19:35:49 -06:00
parent 956b9aca01
commit c8d41b4e69
12 changed files with 318 additions and 114 deletions
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79
openfpga/src/base/openfpga_naming.cpp
View File

@ -569,83 +569,18 @@ std::string generate_grid_duplicated_port_name(const size_t& width,
}
/*********************************************************************
* Generate the port name for a grid in the context of a module
* Generate the port name for a grid in the context of a routing module
* To keep a short and simple name, this function will not
* include any grid coorindate information!
**********************************************************************/
std::string generate_grid_module_port_name(const size_t& pin_id) {
std::string generate_routing_module_grid_port_name(const size_t& width,
const size_t& height,
const int& subtile_index,
const e_side& side,
const BasicPort& pin_info) {
/* For non-top netlist */
std::string port_name = std::string("grid_");
port_name += std::string("pin_");
port_name += std::to_string(pin_id);
port_name += std::string("_");
return port_name;
}
/*********************************************************************
* Generate the port name of a grid pin for a routing module,
* which could be a switch block or a connection block
* Note that to ensure unique grid port name in the context of a routing module,
* we need a prefix which denotes the relative location of the port in the routing module
*
* The prefix is created by considering the the grid coordinate
* and switch block coordinate
* Detailed rules in conversion is as follows:
*
* top_left top_right
* +------------------------+
* left_top | | right_top
* | Switch Block |
* | [x][y] |
* | |
* | |
* left_right | | right_bottom
* +------------------------+
* bottom_left bottom_right
*
* +--------------------------------------------------------
* | Grid Coordinate | Pin side of grid | module side
* +--------------------------------------------------------
* | [x][y+1] | right | top_left
* +--------------------------------------------------------
* | [x][y+1] | bottom | left_top
* +--------------------------------------------------------
* | [x+1][y+1] | left | top_right
* +--------------------------------------------------------
* | [x+1][y+1] | bottom | right_top
* +--------------------------------------------------------
* | [x][y] | top | left_right
* +--------------------------------------------------------
* | [x][y] | right | bottom_left
* +--------------------------------------------------------
* | [x+1][y] | top | right_bottom
* +--------------------------------------------------------
* | [x+1][y] | left | bottom_right
* +--------------------------------------------------------
*
*********************************************************************/
std::string generate_sb_module_grid_port_name(const e_side& sb_side,
const e_side& grid_side,
const size_t& pin_id) {
SideManager sb_side_manager(sb_side);
SideManager grid_side_manager(grid_side);
/* Relative location is opposite to the side in grid context */
grid_side_manager.set_opposite();
std::string prefix = sb_side_manager.to_string() + std::string("_") + grid_side_manager.to_string();
return prefix + std::string("_") + generate_grid_module_port_name(pin_id);
}
/*********************************************************************
* Generate the port name of a grid pin for a routing module,
* which could be a switch block or a connection block
* Note that to ensure unique grid port name in the context of a routing module,
* we need a prefix which denotes the relative location of the port in the routing module
*********************************************************************/
std::string generate_cb_module_grid_port_name(const e_side& cb_side,
const size_t& pin_id) {
SideManager side_manager(cb_side);
std::string prefix = side_manager.to_string();
return prefix + std::string("_") + generate_grid_module_port_name(pin_id);
return port_name + generate_grid_port_name(width, height, subtile_index, side, pin_info);
}
/*********************************************************************

13
openfpga/src/base/openfpga_naming.h
View File

@ -148,14 +148,11 @@ std::string generate_grid_duplicated_port_name(const size_t& width,
const BasicPort& pin_info,
const bool& upper_port);
std::string generate_grid_module_port_name(const size_t& pin_id);
std::string generate_sb_module_grid_port_name(const e_side& sb_side,
const e_side& grid_side,
const size_t& pin_id);
std::string generate_cb_module_grid_port_name(const e_side& cb_side,
const size_t& pin_id);
std::string generate_routing_module_grid_port_name(const size_t& width,
const size_t& height,
const int& subtile_index,
const e_side& side,
const BasicPort& pin_info);
std::string generate_reserved_sram_port_name(const e_circuit_model_port_type& port_type);

117
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -10,6 +10,7 @@
#include "vtr_assert.h"
#include "vtr_geometry.h"
#include "openfpga_side_manager.h"
#include "openfpga_naming.h"
#include "build_routing_module_utils.h"
@ -17,6 +18,104 @@
/* begin namespace openfpga */
namespace openfpga {
/*********************************************************************
* Generate the port name of a grid pin for a routing module,
* which could be a switch block or a connection block
* Note that to ensure unique grid port name in the context of a routing module,
* we need a prefix which denotes the relative location of the port in the routing module
*
* The prefix is created by considering the the grid coordinate
* and switch block coordinate
* Detailed rules in conversion is as follows:
*
* top_left top_right
* +------------------------+
* left_top | | right_top
* | Switch Block |
* | [x][y] |
* | |
* | |
* left_right | | right_bottom
* +------------------------+
* bottom_left bottom_right
*
* +--------------------------------------------------------
* | Grid Coordinate | Pin side of grid | module side
* +--------------------------------------------------------
* | [x][y+1] | right | top_left
* +--------------------------------------------------------
* | [x][y+1] | bottom | left_top
* +--------------------------------------------------------
* | [x+1][y+1] | left | top_right
* +--------------------------------------------------------
* | [x+1][y+1] | bottom | right_top
* +--------------------------------------------------------
* | [x][y] | top | left_right
* +--------------------------------------------------------
* | [x][y] | right | bottom_left
* +--------------------------------------------------------
* | [x+1][y] | top | right_bottom
* +--------------------------------------------------------
* | [x+1][y] | left | bottom_right
* +--------------------------------------------------------
*
*********************************************************************/
std::string generate_sb_module_grid_port_name(const e_side& sb_side,
const e_side& grid_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRNodeId& rr_node) {
SideManager sb_side_manager(sb_side);
SideManager grid_side_manager(grid_side);
/* Relative location is opposite to the side in grid context */
grid_side_manager.set_opposite();
std::string prefix = sb_side_manager.to_string() + std::string("_") + grid_side_manager.to_string();
/* Collect the attributes of the rr_node required to generate the port name */
int pin_id = rr_graph.node_pin_num(rr_node);
e_side pin_side = rr_graph.node_side(rr_node);
t_physical_tile_type_ptr physical_tile = vpr_device_grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)].type;
int pin_width_offset = physical_tile->pin_width_offset[pin_id];
int pin_height_offset = physical_tile->pin_height_offset[pin_id];
BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, pin_id);
VTR_ASSERT(true == pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(physical_tile, pin_id);
VTR_ASSERT(OPEN != subtile_index && subtile_index < physical_tile->capacity);
return prefix + std::string("_") + generate_routing_module_grid_port_name(pin_width_offset, pin_height_offset, subtile_index, pin_side, pin_info);
}
/*********************************************************************
* Generate the port name of a grid pin for a routing module,
* which could be a switch block or a connection block
* Note that to ensure unique grid port name in the context of a routing module,
* we need a prefix which denotes the relative location of the port in the routing module
*********************************************************************/
std::string generate_cb_module_grid_port_name(const e_side& cb_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRNodeId& rr_node) {
SideManager side_manager(cb_side);
std::string prefix = side_manager.to_string();
/* Collect the attributes of the rr_node required to generate the port name */
int pin_id = rr_graph.node_pin_num(rr_node);
e_side pin_side = rr_graph.node_side(rr_node);
t_physical_tile_type_ptr physical_tile = vpr_device_grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)].type;
int pin_width_offset = physical_tile->pin_width_offset[pin_id];
int pin_height_offset = physical_tile->pin_height_offset[pin_id];
BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, pin_id);
VTR_ASSERT(true == pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(physical_tile, pin_id);
VTR_ASSERT(OPEN != subtile_index && subtile_index < physical_tile->capacity);
return prefix + std::string("_") + generate_routing_module_grid_port_name(pin_width_offset, pin_height_offset, subtile_index, pin_side, pin_info);
}
/*********************************************************************
* Find the port id and pin id for a routing track in the switch
* block module with a given rr_node
@ -64,6 +163,8 @@ ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_man
********************************************************************/
ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& input_side,
@ -84,7 +185,10 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma
std::string input_port_name = generate_sb_module_grid_port_name(input_side,
grid_pin_side,
rr_graph.node_pin_num(input_rr_node));
grids,
vpr_device_annotation,
rr_graph,
input_rr_node);
/* Must find a valid port id in the Switch Block module */
input_port.first = module_manager.find_module_port(sb_module, input_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, input_port.first));
@ -109,6 +213,8 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma
********************************************************************/
std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const std::vector<RRNodeId>& input_rr_nodes) {
@ -123,7 +229,7 @@ std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleMana
VTR_ASSERT(NUM_SIDES != input_pin_side);
VTR_ASSERT(-1 != index);
input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_graph, rr_gsb, input_pin_side, input_rr_node));
input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, grids, vpr_device_annotation, rr_graph, rr_gsb, input_pin_side, input_rr_node));
}
return input_ports;
@ -169,6 +275,8 @@ ModulePinInfo find_connection_block_module_chan_port(const ModuleManager& module
********************************************************************/
ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const RRNodeId& src_rr_node) {
@ -184,7 +292,10 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_
/* We need to be sure that drive_rr_node is part of the CB */
VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side));
std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side,
rr_graph.node_pin_num(rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)));
grids,
vpr_device_annotation,
rr_graph,
rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index));
/* Must find a valid port id in the Switch Block module */
ModulePortId ipin_port_id = module_manager.find_module_port(cb_module, port_name);

21
openfpga/src/fabric/build_routing_module_utils.h
View File

@ -10,6 +10,8 @@
#include "rr_gsb.h"
#include "module_manager.h"
#include "vpr_types.h"
#include "device_grid.h"
#include "vpr_device_annotation.h"
/********************************************************************
* Function declaration
@ -20,6 +22,19 @@ namespace openfpga {
typedef std::pair<ModulePortId, size_t> ModulePinInfo;
std::string generate_sb_module_grid_port_name(const e_side& sb_side,
const e_side& grid_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRNodeId& rr_node);
std::string generate_cb_module_grid_port_name(const e_side& cb_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRNodeId& rr_node);
ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,
@ -30,6 +45,8 @@ ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_man
ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& input_side,
@ -37,6 +54,8 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma
std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const std::vector<RRNodeId>& input_rr_nodes);
@ -50,6 +69,8 @@ ModulePinInfo find_connection_block_module_chan_port(const ModuleManager& module
ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const RRNodeId& src_rr_node);

48
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -42,6 +42,8 @@ namespace openfpga {
static
void build_switch_block_module_short_interc(ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
@ -81,7 +83,7 @@ void build_switch_block_module_short_interc(ModuleManager& module_manager,
exit(1);
}
/* Find the name of input port */
ModulePinInfo input_port_info = find_switch_block_module_input_port(module_manager, sb_module, rr_graph, rr_gsb, input_pin_side, drive_rr_node);
ModulePinInfo input_port_info = find_switch_block_module_input_port(module_manager, sb_module, grids, device_annotation, rr_graph, rr_gsb, input_pin_side, drive_rr_node);
/* The input port and output port must match in size */
BasicPort input_port = module_manager.module_port(sb_module, input_port_info.first);
@ -102,6 +104,7 @@ static
void build_switch_block_mux_module(ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const CircuitLibrary& circuit_lib,
@ -137,7 +140,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
module_manager.set_child_instance_name(sb_module, mux_module, mux_instance_id, mux_instance_name);
/* Generate input ports that are wired to the input bus of the routing multiplexer */
std::vector<ModulePinInfo> sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_graph, rr_gsb, driver_rr_nodes);
std::vector<ModulePinInfo> sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, grids, device_annotation, rr_graph, rr_gsb, driver_rr_nodes);
/* Link input bus port to Switch Block inputs */
std::vector<CircuitPortId> mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
@ -211,6 +214,7 @@ static
void build_switch_block_interc_modules(ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const CircuitLibrary& circuit_lib,
@ -234,6 +238,8 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
if (0 == driver_rr_nodes.size()) {
/* Print a special direct connection*/
build_switch_block_module_short_interc(module_manager, sb_module,
device_annotation,
grids,
rr_graph, rr_gsb,
chan_side, cur_rr_node,
cur_rr_node,
@ -241,6 +247,8 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
} else if (1 == driver_rr_nodes.size()) {
/* Print a direct connection*/
build_switch_block_module_short_interc(module_manager, sb_module,
device_annotation,
grids,
rr_graph, rr_gsb, chan_side, cur_rr_node,
driver_rr_nodes[0],
input_port_to_module_nets);
@ -249,7 +257,8 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(rr_graph, cur_rr_node);
VTR_ASSERT(1 == driver_switches.size());
build_switch_block_mux_module(module_manager,
sb_module, device_annotation, rr_graph, rr_gsb,
sb_module, device_annotation,
grids, rr_graph, rr_gsb,
circuit_lib,
chan_side, chan_node_id, cur_rr_node,
driver_rr_nodes,
@ -327,6 +336,7 @@ static
void build_switch_block_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
@ -400,7 +410,10 @@ void build_switch_block_module(ModuleManager& module_manager,
rr_graph.node_ylow(rr_gsb.get_opin_node(side_manager.get_side(), inode)));
std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode)));
grids,
device_annotation,
rr_graph,
rr_gsb.get_opin_node(side_manager.get_side(), inode));
BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */
/* Grid outputs are inputs of switch blocks */
ModulePortId input_port_id = module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_INPUT_PORT);
@ -418,7 +431,8 @@ void build_switch_block_module(ModuleManager& module_manager,
/* We care OUTPUT tracks at this time only */
if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
build_switch_block_interc_modules(module_manager,
sb_module, device_annotation, rr_graph, rr_gsb,
sb_module, device_annotation,
grids, rr_graph, rr_gsb,
circuit_lib,
side_manager.get_side(),
itrack,
@ -469,6 +483,8 @@ void build_switch_block_module(ModuleManager& module_manager,
static
void build_connection_block_module_short_interc(ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -507,7 +523,7 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager,
ModulePinInfo input_port_info = find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_node);
/* Create port description for input pin of a CLB */
ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_graph, rr_gsb, src_rr_node);
ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, grids, device_annotation, rr_graph, rr_gsb, src_rr_node);
/* The input port and output port must match in size */
BasicPort input_port = module_manager.module_port(cb_module, input_port_info.first);
@ -529,6 +545,7 @@ static
void build_connection_block_mux_module(ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -595,7 +612,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0]));
VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id));
BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id);
ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_graph, rr_gsb, cur_rr_node);
ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, grids, device_annotation, rr_graph, rr_gsb, cur_rr_node);
BasicPort cb_output_port = module_manager.module_port(cb_module, cb_output_port_id);
/* Check port size should match */
@ -642,6 +659,7 @@ static
void build_connection_block_interc_modules(ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -655,13 +673,13 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
return; /* This port has no driver, skip it */
} else if (1 == rr_graph.node_in_edges(src_rr_node).size()) {
/* Print a direct connection */
build_connection_block_module_short_interc(module_manager, cb_module, rr_graph, rr_gsb, cb_type, src_rr_node, input_port_to_module_nets);
build_connection_block_module_short_interc(module_manager, cb_module, device_annotation, grids, rr_graph, rr_gsb, cb_type, src_rr_node, input_port_to_module_nets);
} else if (1 < rr_graph.node_in_edges(src_rr_node).size()) {
/* Print the multiplexer, fan_in >= 2 */
build_connection_block_mux_module(module_manager,
cb_module, device_annotation,
rr_graph, rr_gsb, cb_type,
grids, rr_graph, rr_gsb, cb_type,
circuit_lib,
cb_ipin_side, ipin_index,
input_port_to_module_nets);
@ -726,6 +744,7 @@ static
void build_connection_block_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
@ -799,7 +818,10 @@ void build_connection_block_module(ModuleManager& module_manager,
const RRNodeId& ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
vtr::Point<size_t> port_coord(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node));
std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side,
rr_graph.node_pin_num(ipin_node));
grids,
device_annotation,
rr_graph,
ipin_node);
BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */
/* Grid outputs are inputs of switch blocks */
module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT);
@ -838,6 +860,7 @@ void build_connection_block_module(ModuleManager& module_manager,
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
build_connection_block_interc_modules(module_manager,
cb_module, device_annotation,
grids,
rr_graph,
rr_gsb, cb_type,
circuit_lib,
@ -914,6 +937,7 @@ void build_flatten_connection_block_modules(ModuleManager& module_manager,
build_connection_block_module(module_manager,
decoder_lib,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
circuit_lib,
sram_orgz_type, sram_model,
@ -956,6 +980,7 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
build_switch_block_module(module_manager,
decoder_lib,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
circuit_lib,
sram_orgz_type, sram_model,
@ -1014,6 +1039,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
build_switch_block_module(module_manager,
decoder_lib,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
circuit_lib,
sram_orgz_type, sram_model,
@ -1028,6 +1054,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
build_connection_block_module(module_manager,
decoder_lib,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
circuit_lib,
sram_orgz_type, sram_model,
@ -1042,6 +1069,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
build_connection_block_module(module_manager,
decoder_lib,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
circuit_lib,
sram_orgz_type, sram_model,

18
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -23,6 +23,7 @@
#include "openfpga_device_grid_utils.h"
#include "module_manager_utils.h"
#include "build_routing_module_utils.h"
#include "build_top_module_utils.h"
#include "build_top_module_connection.h"
@ -131,10 +132,12 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
/* Collect sink-related information */
vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)),
rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode)));
size_t sink_grid_pin_index = rr_graph.node_pin_num(module_sb.get_opin_node(side_manager.get_side(), inode));
std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)),
sink_grid_pin_index);
grids,
vpr_device_annotation,
rr_graph,
module_sb.get_opin_node(side_manager.get_side(), inode));
ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id));
BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id);
@ -282,10 +285,12 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
/* Collect sink-related information */
vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)),
rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode)));
size_t sink_grid_pin_index = rr_graph.node_pin_num(module_sb.get_opin_node(side_manager.get_side(), inode));
std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)),
sink_grid_pin_index);
grids,
vpr_device_annotation,
rr_graph,
module_sb.get_opin_node(side_manager.get_side(), inode));
ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id));
BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id);
@ -413,7 +418,10 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager,
vtr::Point<size_t> cb_src_port_coord(rr_graph.node_xlow(module_ipin_node),
rr_graph.node_ylow(module_ipin_node));
std::string src_cb_port_name = generate_cb_module_grid_port_name(cb_ipin_side,
rr_graph.node_pin_num(module_ipin_node));
grids,
vpr_device_annotation,
rr_graph,
module_ipin_node);
ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, src_cb_port_id));
BasicPort src_cb_port = module_manager.module_port(src_cb_module, src_cb_port_id);

49
openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp
View File

@ -16,6 +16,7 @@
#include "openfpga_reserved_words.h"
#include "openfpga_naming.h"
#include "build_routing_module_utils.h"
#include "sdc_writer_utils.h"
#include "analysis_sdc_writer_utils.h"
#include "analysis_sdc_routing_writer.h"
@ -33,6 +34,8 @@ static
void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -140,7 +143,10 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
}
std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side,
rr_graph.node_pin_num(ipin_node));
grids,
device_annotation,
rr_graph,
ipin_node);
/* Find the port in unique mirror! */
if (true == compact_routing_hierarchy) {
@ -149,7 +155,10 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, cb_coord);
const RRNodeId& unique_mirror_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode);
port_name = generate_cb_module_grid_port_name(cb_ipin_side,
rr_graph.node_pin_num(unique_mirror_ipin_node));
grids,
device_annotation,
rr_graph,
unique_mirror_ipin_node);
}
/* Ensure we have this port in the module! */
@ -211,6 +220,8 @@ static
void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -233,6 +244,8 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
print_analysis_sdc_disable_cb_unused_resources(fp,
atom_ctx,
module_manager,
device_annotation,
grids,
rr_graph,
routing_annotation,
device_rr_gsb,
@ -250,6 +263,8 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -257,6 +272,8 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
print_analysis_sdc_disable_unused_cb_ports(fp, atom_ctx,
module_manager,
device_annotation,
grids,
rr_graph,
routing_annotation,
device_rr_gsb,
@ -264,6 +281,8 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
print_analysis_sdc_disable_unused_cb_ports(fp, atom_ctx,
module_manager,
device_annotation,
grids,
rr_graph,
routing_annotation,
device_rr_gsb,
@ -280,6 +299,8 @@ static
void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -370,7 +391,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(opin_node),
rr_graph.node_pin_num(opin_node));
grids,
device_annotation,
rr_graph,
opin_node);
if (true == compact_routing_hierarchy) {
/* Note: use GSB coordinate when inquire for unique modules!!! */
@ -380,7 +404,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(unique_mirror_opin_node),
rr_graph.node_pin_num(unique_mirror_opin_node));
grids,
device_annotation,
rr_graph,
unique_mirror_opin_node);
}
@ -432,7 +459,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(opin_node),
rr_graph.node_pin_num(opin_node));
grids,
device_annotation,
rr_graph,
opin_node);
if (true == compact_routing_hierarchy) {
/* Note: use GSB coordinate when inquire for unique modules!!! */
@ -442,7 +472,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(unique_mirror_opin_node),
rr_graph.node_pin_num(unique_mirror_opin_node));
grids,
device_annotation,
rr_graph,
unique_mirror_opin_node);
}
@ -512,6 +545,8 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -534,6 +569,8 @@ void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
print_analysis_sdc_disable_sb_unused_resources(fp,
atom_ctx,
module_manager,
device_annotation,
grids,
rr_graph,
routing_annotation,
device_rr_gsb,

5
openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
View File

@ -8,6 +8,7 @@
#include <vector>
#include "vpr_context.h"
#include "module_manager.h"
#include "device_grid.h"
#include "device_rr_gsb.h"
#include "vpr_routing_annotation.h"
@ -21,6 +22,8 @@ namespace openfpga {
void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -29,6 +32,8 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,

4
openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
View File

@ -267,6 +267,8 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
print_analysis_sdc_disable_unused_cbs(fp,
vpr_ctx.atom(),
openfpga_ctx.module_graph(),
openfpga_ctx.vpr_device_annotation(),
vpr_ctx.device().grid,
vpr_ctx.device().rr_graph,
openfpga_ctx.vpr_routing_annotation(),
openfpga_ctx.device_rr_gsb(),
@ -276,6 +278,8 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
print_analysis_sdc_disable_unused_sbs(fp,
vpr_ctx.atom(),
openfpga_ctx.module_graph(),
openfpga_ctx.vpr_device_annotation(),
vpr_ctx.device().grid,
vpr_ctx.device().rr_graph,
openfpga_ctx.vpr_routing_annotation(),
openfpga_ctx.device_rr_gsb(),

40
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
View File

@ -55,6 +55,8 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
const std::string& module_path,
const ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& output_node_side,
@ -78,6 +80,8 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
/* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */
std::vector<ModulePinInfo> module_input_ports = find_switch_block_module_input_ports(module_manager,
sb_module,
grids,
device_annotation,
rr_graph,
rr_gsb,
get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node));
@ -143,6 +147,8 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
const bool& hierarchical,
const std::string& module_path,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const bool& constrain_zero_delay_paths) {
@ -186,6 +192,8 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
hierarchical,
module_path,
module_manager, sb_module,
device_annotation,
grids,
rr_graph,
rr_gsb,
side_manager.get_side(),
@ -207,6 +215,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
@ -239,6 +249,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
hierarchical,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
rr_gsb,
constrain_zero_delay_paths);
@ -255,6 +267,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
@ -286,6 +300,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
hierarchical,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
rr_gsb,
constrain_zero_delay_paths);
@ -303,6 +319,8 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
const std::string& module_path,
const ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -338,6 +356,8 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
/* Find the module port corresponding to the output rr_node */
ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager,
cb_module,
grids,
device_annotation,
rr_graph,
rr_gsb,
output_rr_node);
@ -405,6 +425,8 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
const bool& hierarchical,
const std::string& module_path,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -499,6 +521,8 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
time_unit,
hierarchical, module_path,
module_manager, cb_module,
device_annotation,
grids,
rr_graph, rr_gsb, cb_type,
ipin_rr_node,
constrain_zero_delay_paths);
@ -519,6 +543,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const t_rr_type& cb_type,
@ -554,6 +580,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
hierarchical,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
rr_gsb,
cb_type,
@ -572,6 +600,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
@ -582,6 +612,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, time_unit,
hierarchical,
module_manager, top_module,
device_annotation,
grids,
rr_graph,
device_rr_gsb,
CHANX,
@ -590,6 +622,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, time_unit,
hierarchical,
module_manager, top_module,
device_annotation,
grids,
rr_graph,
device_rr_gsb,
CHANY,
@ -605,6 +639,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
@ -633,6 +669,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
hierarchical,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
unique_mirror,
CHANX,
@ -658,6 +696,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
hierarchical,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
unique_mirror,
CHANY,

10
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
View File

@ -9,6 +9,8 @@
#include "module_manager.h"
#include "device_rr_gsb.h"
#include "rr_graph_obj.h"
#include "device_grid.h"
#include "vpr_device_annotation.h"
/********************************************************************
* Function declaration
@ -22,6 +24,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);
@ -31,6 +35,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);
@ -40,6 +46,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);
@ -49,6 +57,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);

8
openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
View File

@ -382,6 +382,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
sdc_options.hierarchical(),
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());
@ -392,6 +394,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
sdc_options.hierarchical(),
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());
@ -416,6 +420,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
sdc_options.hierarchical(),
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());
@ -426,6 +432,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
sdc_options.hierarchical(),
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());