start using counter benchmark in regression tests

openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v

@@ -0,0 +1,84 @@
+/* Generated by Yosys 0.9 (git sha1 f110c953, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */
+
+module counter(clk_counter, rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] , \q_counter[6] , \q_counter[7] );
+  wire _00_;
+  wire _01_;
+  input clk_counter;
+  wire n22;
+  wire n26;
+  wire n30;
+  wire n34;
+  wire n38;
+  wire n42;
+  wire n46;
+  wire n50;
+  output \q_counter[0] ;
+  reg \q_counter[0] ;
+  output \q_counter[1] ;
+  reg \q_counter[1] ;
+  output \q_counter[2] ;
+  reg \q_counter[2] ;
+  output \q_counter[3] ;
+  reg \q_counter[3] ;
+  output \q_counter[4] ;
+  reg \q_counter[4] ;
+  output \q_counter[5] ;
+  reg \q_counter[5] ;
+  output \q_counter[6] ;
+  reg \q_counter[6] ;
+  output \q_counter[7] ;
+  reg \q_counter[7] ;
+  input rst_counter;
+  
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[0] <= 1'b0;
+    else \q_counter[0]  <= n22;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[1] <= 1'b0;
+    else \q_counter[1]  <= n26;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[2] <= 1'b0;
+    else \q_counter[2]  <= n30;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[3] <= 1'b0;
+    else \q_counter[3]  <= n34;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[4] <= 1'b0;
+    else \q_counter[4]  <= n38;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[5] <= 1'b0;
+    else \q_counter[5]  <= n42;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[6] <= 1'b0;
+    else \q_counter[6]  <= n46;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[7] <= 1'b0;
+    else \q_counter[7]  <= n50;
+  end
+  
+  assign n26 = 8'h14 >> { \q_counter[0] , \q_counter[1] , rst_counter };
+  assign n30 = 16'h0708 >> { \q_counter[2] , rst_counter, \q_counter[0] , \q_counter[1]  };
+  assign n34 = 32'd8323200 >> { \q_counter[3] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2]  };
+  assign n38 = 64'h00007fff00008000 >> { \q_counter[4] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3]  };
+  assign n42 = 8'h14 >> { _00_, \q_counter[5] , rst_counter };
+  assign _00_ = 32'd2147483648 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4]  };
+  assign n46 = 8'h14 >> { _01_, \q_counter[6] , rst_counter };
+  assign _01_ = 64'h8000000000000000 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5]  };
+  assign n50 = 16'h0708 >> { \q_counter[7] , rst_counter, _01_, \q_counter[6]  };
+  assign n22 = 4'h1 >> { \q_counter[0] , rst_counter };
+endmodule

openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif

@@ -0,0 +1,69 @@
+# Generated by Yosys 0.9 (git sha1 UNKNOWN, clang 7.0.0 -fPIC -Os)
+
+.model counter
+.inputs clk_counter rst_counter
+.outputs q_counter[0] q_counter[1] q_counter[2] q_counter[3] q_counter[4] q_counter[5] q_counter[6] q_counter[7]
+.names $false
+.names $true
+1
+.names $undef
+.names q_counter[7] rst_counter q_counter[6] $abc$3686$new_n20_ $0\q_counter[7][0:0]
+0011 1
+1000 1
+1001 1
+1010 1
+.names q_counter[4] q_counter[5] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n20_
+111111 1
+.names q_counter[6] $abc$3686$new_n20_ rst_counter $0\q_counter[6][0:0]
+010 1
+100 1
+.names q_counter[5] $abc$3686$new_n23_ rst_counter $0\q_counter[5][0:0]
+010 1
+100 1
+.names q_counter[4] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n23_
+11111 1
+.names q_counter[2] rst_counter q_counter[1] q_counter[0] $0\q_counter[2][0:0]
+0011 1
+1000 1
+1001 1
+1010 1
+.names q_counter[4] rst_counter q_counter[3] q_counter[2] q_counter[1] q_counter[0] $0\q_counter[4][0:0]
+001111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+.names q_counter[3] rst_counter q_counter[2] q_counter[1] q_counter[0] $0\q_counter[3][0:0]
+00111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+.names q_counter[1] q_counter[0] rst_counter $0\q_counter[1][0:0]
+010 1
+100 1
+.names q_counter[0] rst_counter $0\q_counter[0][0:0]
+00 1
+.latch $0\q_counter[7][0:0] q_counter[7] re clk_counter 2
+.latch $0\q_counter[6][0:0] q_counter[6] re clk_counter 2
+.latch $0\q_counter[5][0:0] q_counter[5] re clk_counter 2
+.latch $0\q_counter[4][0:0] q_counter[4] re clk_counter 2
+.latch $0\q_counter[3][0:0] q_counter[3] re clk_counter 2
+.latch $0\q_counter[2][0:0] q_counter[2] re clk_counter 2
+.latch $0\q_counter[1][0:0] q_counter[1] re clk_counter 2
+.latch $0\q_counter[0][0:0] q_counter[0] re clk_counter 2
+.end

openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act

@@ -0,0 +1,20 @@
+clk_counter 0.500000 2.000000
+rst_counter 0.492200 0.201800
+q_counter[0] 0.281800 0.563400
+q_counter[1] 0.248200 0.273600
+q_counter[2] 0.183200 0.125600
+q_counter[3] 0.097400 0.044800
+q_counter[4] 0.022600 0.007200
+q_counter[5] 0.002200 0.000800
+q_counter[6] 0.000000 0.000000
+q_counter[7] 0.000000 0.000000
+$0\q_counter[7][0:0] 0 0
+$0\q_counter[6][0:0] 0 0
+$0\q_counter[5][0:0] 0 0
+$0\q_counter[4][0:0] 0 0
+$0\q_counter[3][0:0] 0 0
+$0\q_counter[2][0:0] 0 0
+$0\q_counter[1][0:0] 0 0
+$0\q_counter[0][0:0] 0 0
+$abc$3686$new_n23_ 0 0
+$abc$3686$new_n20_ 0 0

openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf

@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = and2
+bench0_top = counter
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]