riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

fixed a critical bug when instanciating Connection blocks

This commit is contained in:
tangxifan 2019-06-26 11:33:02 -06:00
parent d50fb7ee19
commit c879e7f6c5
3 changed files with 22 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
View File

@ -262,8 +262,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
* 1. a compact output * 1. a compact output
* 2. a full-size output * 2. a full-size output
*/ */
dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, lb_dir_path, &Arch, dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, lb_dir_path, &Arch);
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
/* Dump internal structures of submodules */ /* Dump internal structures of submodules */
dump_verilog_submodules(sram_verilog_orgz_info, src_dir_path, submodule_dir_path, dump_verilog_submodules(sram_verilog_orgz_info, src_dir_path, submodule_dir_path,
@ -275,7 +274,6 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
top_netlist_path, src_dir_path, submodule_dir_path, lb_dir_path, rr_dir_path, top_netlist_path, src_dir_path, submodule_dir_path, lb_dir_path, rr_dir_path,
num_rr_nodes, rr_node, rr_node_indices, num_rr_nodes, rr_node, rr_node_indices,
num_clocks, num_clocks,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts,
vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy,
*(Arch.spice)); *(Arch.spice));

43
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -281,9 +281,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
char* verilog_dir_path, char* verilog_dir_path,
char* subckt_dir_path, char* subckt_dir_path,
t_type_ptr phy_block_type, t_type_ptr phy_block_type,
int border_side, int border_side) {
t_arch* arch,
t_syn_verilog_opts fpga_verilog_opts) {
int iz; int iz;
int temp_reserved_conf_bits_msb; int temp_reserved_conf_bits_msb;
int temp_iopad_lsb, temp_iopad_msb; int temp_iopad_lsb, temp_iopad_msb;
@ -514,8 +512,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* verilog_dir,
char* subckt_dir, char* subckt_dir,
t_arch* arch, t_arch* arch) {
t_syn_verilog_opts fpga_verilog_opts) {
int itype, iside, num_sides; int itype, iside, num_sides;
int* stamped_spice_model_cnt = NULL; int* stamped_spice_model_cnt = NULL;
t_sram_orgz_info* stamped_sram_orgz_info = NULL; t_sram_orgz_info* stamped_sram_orgz_info = NULL;
@ -537,23 +534,20 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
for (iside = 0; iside < num_sides; iside++) { for (iside = 0; iside < num_sides; iside++) {
dump_compact_verilog_one_physical_block(cur_sram_orgz_info, dump_compact_verilog_one_physical_block(cur_sram_orgz_info,
verilog_dir, subckt_dir, verilog_dir, subckt_dir,
&type_descriptors[itype], iside, &type_descriptors[itype], iside);
arch, fpga_verilog_opts);
} }
continue; continue;
} else if (FILL_TYPE == &type_descriptors[itype]) { } else if (FILL_TYPE == &type_descriptors[itype]) {
/* For CLB */ /* For CLB */
dump_compact_verilog_one_physical_block(cur_sram_orgz_info, dump_compact_verilog_one_physical_block(cur_sram_orgz_info,
verilog_dir, subckt_dir, verilog_dir, subckt_dir,
&type_descriptors[itype], -1, &type_descriptors[itype], -1);
arch, fpga_verilog_opts);
continue; continue;
} else { } else {
/* For heterogenenous blocks */ /* For heterogenenous blocks */
dump_compact_verilog_one_physical_block(cur_sram_orgz_info, dump_compact_verilog_one_physical_block(cur_sram_orgz_info,
verilog_dir, subckt_dir, verilog_dir, subckt_dir,
&type_descriptors[itype], -1, &type_descriptors[itype], -1);
arch, fpga_verilog_opts);
} }
} }
@ -975,7 +969,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_
static static
void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) { FILE* fp) {
int ix, iy; DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
/* Check the file handler*/ /* Check the file handler*/
if (NULL == fp) { if (NULL == fp) {
@ -984,21 +978,23 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
exit(1); exit(1);
} }
/* X - channels [1...nx][0..ny]*/ /* Walk through GSBs */
for (iy = 0; iy < (ny + 1); iy++) { for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (ix = 1; ix < (nx + 1); ix++) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
if ((TRUE == is_cb_exist(CHANX, ix, iy))
/* Get X-channel CB coordinator */
const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX);
/* X - channels [1...nx][0..ny]*/
if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x()))
&&(true == rr_gsb.is_cb_exist(CHANX))) { &&(true == rr_gsb.is_cb_exist(CHANX))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX); dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX);
} }
}
} /* Get X-channel CB coordinator */
/* Y - channels [1...ny][0..nx]*/ const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY);
for (ix = 0; ix < (nx + 1); ix++) { /* Y - channels [1...ny][0..nx]*/
for (iy = 1; iy < (ny + 1); iy++) { if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x()))
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
if ((TRUE == is_cb_exist(CHANY, ix, iy))
&&(true == rr_gsb.is_cb_exist(CHANY))) { &&(true == rr_gsb.is_cb_exist(CHANY))) {
dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY); dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY);
} }
@ -1180,7 +1176,6 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* LL_rr_node, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices, t_ivec*** LL_rr_node_indices,
int num_clock, int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy, boolean compact_routing_hierarchy,
t_spice verilog) { t_spice verilog) {
FILE* fp = NULL; FILE* fp = NULL;

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h
View File

@ -5,15 +5,12 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf
char* verilog_dir_path, char* verilog_dir_path,
char* subckt_dir_path, char* subckt_dir_path,
t_type_ptr phy_block_type, t_type_ptr phy_block_type,
int border_side, int border_side);
t_arch* arch,
t_syn_verilog_opts fpga_verilog_opts);
void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* verilog_dir,
char* subckt_dir, char* subckt_dir,
t_arch* arch, t_arch* arch);
t_syn_verilog_opts fpga_verilog_opts);
void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name, char* circuit_name,
@ -26,7 +23,6 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* LL_rr_node, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices, t_ivec*** LL_rr_node_indices,
int num_clock, int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
boolean compact_routing_hierarchy, boolean compact_routing_hierarchy,
t_spice verilog); t_spice verilog);
#endif #endif