riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Removed files after regression test

This commit is contained in:
Ganesh Gore 2019-11-02 17:55:36 -06:00
parent d14be73825
commit c80cbfe8c9
2 changed files with 8 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.travis.yml
View File

@ -55,7 +55,7 @@ before_install:
- eval "$(ssh-agent -s)"
- chmod 600 ./deploy_key
- cp $TRAVIS_BUILD_DIR/deploy_key ~/.ssh/id_rsa
- echo -e "Host github.com\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
- echo -e "Host *\n StrictHostKeyChecking no\n" >> ~/.ssh/config
- ssh u1249762@lab1-1.eng.utah.edu pwd
- ssh u1249762@lab1-1.eng.utah.edu "mkdir /var/tmp/travis_bc/$TRAVIS_JOB_ID"
- echo $TRAVIS_JOB_ID >> build_id.txt

9
.travis/script.sh
View File

@ -19,19 +19,24 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
echo -e "Testing single-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py single_mode
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --remove_run_dir all
#python3 openfpga_flow/scripts/run_fpga_task.py s298
echo -e "Testing multi-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 2
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --remove_run_dir all
echo -e "Testing compact routing techniques";
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --remove_run_dir all
echo -e "Testing tileable architectures";
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --remove_run_dir all
echo -e "Testing Verilog generation with explicit port mapping ";
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --remove_run_dir all
end_section "OpenFPGA.TaskTun"