From c7e1f7d90b1b7ffbea6eb98880dc5829102b0ad0 Mon Sep 17 00:00:00 2001
From: Baudouin Chauviere <baudouin.chauviere@utah.edu>
Date: Thu, 3 Oct 2019 10:17:04 -0600
Subject: [PATCH] Added explicit_verilog to regression test in a clean way

---
 .travis/script.sh                             |  2 +-
 .../tasks/blif_vpr_flow/config/task.conf      |  5 +--
 .../tasks/explicit_verilog/config/task.conf   | 41 +++++++++++++++++++
 3 files changed, 44 insertions(+), 4 deletions(-)
 create mode 100644 openfpga_flow/tasks/explicit_verilog/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index fa9e95ea8..37e96e1a8 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -18,5 +18,5 @@ end_section "OpenFPGA.build"
 
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd -
-python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing --maxthreads 2
+python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 2
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf
index cf283f22a..d3fc4fedc 100644
--- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf
+++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf
@@ -64,7 +64,7 @@ vpr_fpga_verilog_print_sdc_analysis=
 end_flow_with_test=
 
 
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT]
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_COMPACT]
 fix_route_chan_width=300
 vpr_fpga_verilog_include_icarus_simulator=
 vpr_fpga_verilog_formal_verification_top_netlist=
@@ -76,6 +76,5 @@ vpr_fpga_verilog_print_user_defined_template=
 vpr_fpga_verilog_print_report_timing_tcl=
 vpr_fpga_verilog_print_sdc_pnr=
 vpr_fpga_verilog_print_sdc_analysis=
-vpr_fpga_x2p_compact_routing_hierarchy=
-vpr_fpga_verilog_explicit_mapping= 
+#vpr_fpga_x2p_compact_routing_hierarchy=
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/explicit_verilog/config/task.conf b/openfpga_flow/tasks/explicit_verilog/config/task.conf
new file mode 100644
index 000000000..be4320161
--- /dev/null
+++ b/openfpga_flow/tasks/explicit_verilog/config/task.conf
@@ -0,0 +1,41 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[ARCHITECTURES]
+arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = test_modes
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT]
+fix_route_chan_width=300
+vpr_fpga_verilog_include_icarus_simulator=
+vpr_fpga_verilog_formal_verification_top_netlist=
+vpr_fpga_verilog_include_timing=
+vpr_fpga_verilog_include_signal_init=
+vpr_fpga_verilog_print_autocheck_top_testbench=
+vpr_fpga_bitstream_generator=
+vpr_fpga_verilog_print_user_defined_template=
+vpr_fpga_verilog_print_report_timing_tcl=
+vpr_fpga_x2p_compact_routing_hierarchy=
+vpr_fpga_verilog_explicit_mapping= 
+end_flow_with_test=