Clean codes
This commit is contained in:
Xifan Tang
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{
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"cells": [
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"# Getting Started with Jupyter and FPGA-SPICE on Linux\n",
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"\n",
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"1. Install Anaconda: https://conda.io/docs/user-guide/install/linux.html \n",
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"2. Run anaconda-navigator: `~/anaconda-navigator`\n",
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"3. Launch jupyter notebook from anaconda navigator\n",
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"\n",
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"In the jupyter interface, navigate to the location of a notebook and view it."
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"The repository contains a submodule, so you need to get it as well:"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Build the VPR tool with the FPGA-SPICE functionality:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 38,
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"metadata": {
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"scrolled": true
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},
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"outputs": [
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{
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"name": "stdout",
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"output_type": "stream",
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"text": [
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"Wait for make to finish with a return code of 0.\n"
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]
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},
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{
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"data": {
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"text/plain": [
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"0"
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]
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},
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"execution_count": 38,
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"metadata": {},
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"output_type": "execute_result"
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}
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],
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"source": [
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"import os\n",
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"# move to the directory with the Makefile\n",
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"os.chdir(\"./tangxifan-eda-tools/branches/vpr7_rram/vpr/\")\n",
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"# run make\n",
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"print (\"Wait for make to finish with a return code of 0.\")\n",
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"os.system(\"make\")"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"To run FPGA-SPICE, define its location:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 30,
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"metadata": {},
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"outputs": [],
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"source": [
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"# set this to the location of the vpr executable file\n",
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"fpga_spice = \"~/OpenFPGA/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr\""
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Define an architecture file and a circuit file:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 31,
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"metadata": {},
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"outputs": [],
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"source": [
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"arch = \"./tutorial/example_arch.xml\"\n",
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"circuit = \"./tutorial/example_circuit.blif\""
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Run vpr:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 35,
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"metadata": {},
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"outputs": [
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{
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"data": {
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"text/plain": [
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"0"
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]
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},
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"execution_count": 35,
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"metadata": {},
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"output_type": "execute_result"
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}
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],
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"source": [
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"\n",
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"command_line = fpga_spice + \" \" + arch + \" \" + circuit\n",
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"os.system(command_line)"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"This will bring up a graphical display of how the circuit is being placed on the FPGA. Press the `Proceed` button to step to the final placement, press `Proceed` again to step to the routing. Press the `Exit` button to exit the display.\n",
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"\n",
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"To run VPR without the display, use the command `-nodisp`"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 33,
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"metadata": {},
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"outputs": [],
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"source": [
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"command_line_nodisp = command_line + \" -nodisp\"\n"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 36,
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"metadata": {},
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"outputs": [
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{
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"data": {
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"text/plain": [
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"0"
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]
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},
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"execution_count": 36,
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"metadata": {},
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"output_type": "execute_result"
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}
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],
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"source": [
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"os.system(command_line_nodisp)"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"When you ran the tool, a number of text output files are created that report on what the tool did. Open the file \"OpenFPGA/tutorial/example_circuit.place\" in a text editor and note on line 2: \n",
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"\n",
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"> `Array size: 2 x 2 logic blocks`\n",
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"\n",
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"This is a report that when the tool placed and routed the logic, it ended up in a 2 x 2 grid."
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Now open the file \"OpenFPGA/tutorial/example_arch.xml\" in a text editor. Go to line 5 and change:\n",
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"\n",
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"<pb_type name=\"io\" capacity=\"1\">\n",
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"\n",
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"to:\n",
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"\n",
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"<pb_type name=\"io\" capacity=\"3\">\n",
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"\n",
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"Now, instead of each input/output block only having 1 input or output, they can have 3 inputs or outputs.\n",
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"\n",
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"Run the tool again:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 34,
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"metadata": {},
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"outputs": [
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{
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"data": {
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"text/plain": [
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"0"
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]
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},
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"execution_count": 34,
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"metadata": {},
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"output_type": "execute_result"
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}
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],
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"source": [
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"os.system(command_line_nodisp)"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Re-open the file \"OpenFPGA/tutorial/example_circuit.place\" in a text editor and note that the logic is now placed in one block:\n",
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"\n",
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"> `Array size: 1 x 1 logic blocks`\n",
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"\n",
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"The simple change to the number of inputs or outputs per I/O block let the placement and routing tool use less space on the FPGA for the circuit."
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"# Changing the Architecture\n",
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"We'll make some changes to the architecture file and see how the output changes. To begin, set up the location of the vpr executable, the input files, and the vpr options. Then run the tool:"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 45,
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"metadata": {},
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"outputs": [
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{
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"data": {
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"text/plain": [
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"0"
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]
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},
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"execution_count": 45,
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"metadata": {},
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"output_type": "execute_result"
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}
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],
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"source": [
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"# set this to the location of the vpr executable file\n",
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"vpr = \"~/vtr-verilog-to-routing/vpr/vpr\"\n",
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"arch = \"~/OpenFPGA/tutorial/v8_example_arch.xml\"\n",
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"circuit = \"~/OpenFPGA/tutorial/example_circuit.blif\"\n",
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"# turn on the graphic display\n",
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"options = \"--disp on\"\n",
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"# set up the command line\n",
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"command_line = vpr + \" \" + arch + \" \" + circuit + \" \" + options\n",
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"\n",
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"import os\n",
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"os.system(command_line)\n"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"That will bring up a display of the FPGA and how the circuit was laid out. Press `Proceed` twice to step through the complete tool cycle, or just press `Exit` to quit.\n",
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"\n",
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"You can see that there are I/O blocks around the perimeter of the layout and a 2x2 grid of complex logic blocks (clb) in the center. Currently, each I/O block only allows for one connection in or out. Our circuit `example_circuit.blif` specifies 3 inputs and 4 outputs, so we should be able to reduce the number of I/O blocks by enabling more that one input or output on each block.\n",
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"\n",
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"Open the architecture file `~/OpenFPGA/tutorial/v8_example_arch.xml`, go to line 58 and change `capacity=1` to `capacity=3`. Run the tool again."
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {},
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"outputs": [],
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"source": [
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"import os\n",
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"os.system(command_line)"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Now the I/O blocks around the perimeter have 3 slots for an input or 3 slots for an output. \n",
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"\n",
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"Currently, the architecture only has one basic logic element (ble) in each clb. Let's change the architecture to put four bles in a clb. Go to line 111 and change `<output name=\"O\" num_pins=\"1\"/>` to `<output name=\"O\" num_pins=\"4\"/>`. That will change the number of ouput pins in the clb.\n",
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"\n",
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"At line 117 change `<pb_type name=\"ble4\" num_pb=\"1\">` to `<pb_type name=\"ble4\" num_pb=\"4\">`. That puts 4 bles in the clb. Note that the ble is named `ble4` and continue to the `<interconnect>` section on lines 162-168.\n",
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"\n",
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"In the `<interconnect>` on lines 161-167 change all instances of `ble4[0:0]` to `ble4[3:0]`. That wires up all four of the bles inside the clb.\n",
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"\n",
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"Run the tool again."
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]
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},
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{
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"cell_type": "code",
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"execution_count": 42,
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"metadata": {},
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"outputs": [
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{
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"data": {
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"text/plain": [
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"0"
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]
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},
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"execution_count": 42,
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"metadata": {},
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"output_type": "execute_result"
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}
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],
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"source": [
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"import os\n",
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"os.system(command_line)"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {},
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"outputs": [],
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"source": []
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {},
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"outputs": [],
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"source": []
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}
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],
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"metadata": {
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"kernelspec": {
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"display_name": "Python 3",
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"language": "python",
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"name": "python3"
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},
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"language_info": {
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"codemirror_mode": {
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"name": "ipython",
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"version": 3
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},
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"file_extension": ".py",
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"mimetype": "text/x-python",
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"name": "python",
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"nbconvert_exporter": "python",
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"pygments_lexer": "ipython3",
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"version": "3.6.5"
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}
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},
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"nbformat": 4,
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"nbformat_minor": 2
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}
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