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[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA

This commit is contained in:
tangxifan 2020-11-30 18:02:00 -07:00
parent ff53d2c375
commit c7604ab94f
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -181,7 +181,7 @@
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="input" prefix="prog_reset" lib_name="RST" size="1" is_global="true" default_val="0" is_prog="true" is_reset="true"/>
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_prog="true" is_reset="true"/>
</circuit_model>
<circuit_model type="iopad" name="EMBEDDED_IO_ISOLN" prefix="EMBEDDED_IO_ISOLN" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
<design_technology type="cmos"/>