Merge branch 'ganesh_dev' into dev

openfpga_flow/OpenFPGAShellScripts/example_script.openfpga

@@ -37,7 +37,7 @@ build_fabric_bitstream --verbose
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file ./VerilogNetlist/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists
@@ -45,14 +45,17 @@ write_fabric_verilog --file ./VerilogNetlist/SRC --explicit_port_mapping --inclu
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./VerilogNetlist/SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
-write_pnr_sdc --file ./VerilogNetlist/SDC
+write_pnr_sdc --file ./SDC
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file ./VerilogNetlist/SDC_analysis
+write_analysis_sdc --file ./SDC_analysis
 
 # Finish and exit OpenFPGA
 exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/scripts/run_fpga_flow.py

@@ -398,7 +398,7 @@ def prepare_run_directory(run_dir):
     # Clean run_dir is created change working directory
     os.chdir(run_dir)
 
-    # Create arch dir in run_dir and copy flattern architecrture file
+    # Create arch dir in run_dir and copy flattened architecture file
     os.mkdir("arch")
     tmpl = Template(
         open(args.arch_file, encoding='utf-8').read())
@@ -407,7 +407,15 @@ def prepare_run_directory(run_dir):
     with open(args.arch_file, 'w', encoding='utf-8') as archfile:
         archfile.write(tmpl.substitute(script_env_vars["PATH"]))
 
-    # Create benchmark dir in run_dir and copy flattern architecrture file
+    if (args.openfpga_arch_file):
+        tmpl = Template(
+            open(args.openfpga_arch_file, encoding='utf-8').read())
+        arch_filename = os.path.basename(args.openfpga_arch_file)
+        args.openfpga_arch_file = os.path.join(run_dir, "arch", arch_filename)
+        with open(args.openfpga_arch_file, 'w', encoding='utf-8') as archfile:
+            archfile.write(tmpl.substitute(script_env_vars["PATH"]))
+
+    # Create benchmark dir in run_dir and copy flattern architecture file
     os.mkdir("benchmark")
     try:
         for index, eachfile in enumerate(args.benchmark_files):

openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf

@@ -30,4 +30,4 @@ bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-min_route_chan_width=1.3
+end_flow_with_test=